Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100518776	1			T1	242269		T3	162074		T4	8360
all_values[1]	100518776	1			T1	242269		T3	162074		T4	8360
all_values[2]	100518776	1			T1	242269		T3	162074		T4	8360

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

496336

1

T1

6817

T3

14

T4

869

auto[1]

301059992

1

T1

719990

T3

486208

T4

24211

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300016839

1

T1

724800

T3

484815

T4

24423

auto[1]

1539489

1

T1

2007

T3

1407

T4

657

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	139067	1			T1	1757		T3	1		T4	238
all_values[0]	auto[0]	auto[1]	1989	1			T1	14		T3	2		T4	14
all_values[0]	auto[1]	auto[0]	99866546	1			T1	239843		T3	161604		T4	7903
all_values[0]	auto[1]	auto[1]	511174	1			T1	655		T3	467		T4	205
all_values[1]	auto[0]	auto[0]	160239	1			T1	1813		T4	229		T30	1
all_values[1]	auto[0]	auto[1]	1548	1			T1	12		T4	9		T30	2
all_values[1]	auto[1]	auto[0]	99845374	1			T1	239787		T3	161605		T4	7912
all_values[1]	auto[1]	auto[1]	511615	1			T1	657		T3	469		T4	210
all_values[2]	auto[0]	auto[0]	191805	1			T1	3211		T3	6		T4	372
all_values[2]	auto[0]	auto[1]	1688	1			T1	10		T3	5		T4	7
all_values[2]	auto[1]	auto[0]	99813808	1			T1	238389		T3	161599		T4	7769
all_values[2]	auto[1]	auto[1]	511475	1			T1	659		T3	464		T4	212