Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
386910 |
1 |
|
|
T1 |
558 |
|
T3 |
2 |
|
T4 |
56 |
auto[1] |
311804 |
1 |
|
|
T1 |
426 |
|
T3 |
618 |
|
T4 |
270 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
175132 |
1 |
|
|
T1 |
204 |
|
T3 |
164 |
|
T4 |
77 |
lower_val |
172850 |
1 |
|
|
T1 |
273 |
|
T3 |
145 |
|
T4 |
90 |
zero_val |
1896 |
1 |
|
|
T1 |
10 |
|
T3 |
3 |
|
T4 |
6 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
270948 |
1 |
|
|
T1 |
358 |
|
T3 |
146 |
|
T4 |
98 |
lower_val |
271014 |
1 |
|
|
T1 |
408 |
|
T3 |
130 |
|
T4 |
76 |
zero_val |
156752 |
1 |
|
|
T1 |
218 |
|
T3 |
344 |
|
T4 |
152 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
48465 |
1 |
|
|
T1 |
60 |
|
T4 |
5 |
|
T31 |
561 |
higher_val |
higher_val |
auto[1] |
19467 |
1 |
|
|
T1 |
20 |
|
T3 |
36 |
|
T4 |
14 |
higher_val |
lower_val |
auto[0] |
48358 |
1 |
|
|
T1 |
56 |
|
T4 |
6 |
|
T31 |
561 |
higher_val |
lower_val |
auto[1] |
19538 |
1 |
|
|
T1 |
30 |
|
T3 |
42 |
|
T4 |
13 |
higher_val |
zero_val |
auto[0] |
96 |
1 |
|
|
T1 |
2 |
|
T59 |
1 |
|
T5 |
1 |
higher_val |
zero_val |
auto[1] |
39208 |
1 |
|
|
T1 |
36 |
|
T3 |
86 |
|
T4 |
39 |
lower_val |
higher_val |
auto[0] |
47831 |
1 |
|
|
T1 |
60 |
|
T4 |
9 |
|
T31 |
560 |
lower_val |
higher_val |
auto[1] |
19145 |
1 |
|
|
T1 |
31 |
|
T3 |
33 |
|
T4 |
13 |
lower_val |
lower_val |
auto[0] |
48065 |
1 |
|
|
T1 |
71 |
|
T4 |
11 |
|
T31 |
589 |
lower_val |
lower_val |
auto[1] |
19339 |
1 |
|
|
T1 |
44 |
|
T3 |
29 |
|
T4 |
14 |
lower_val |
zero_val |
auto[0] |
77 |
1 |
|
|
T1 |
1 |
|
T4 |
2 |
|
T188 |
1 |
lower_val |
zero_val |
auto[1] |
38393 |
1 |
|
|
T1 |
66 |
|
T3 |
83 |
|
T4 |
41 |
zero_val |
higher_val |
auto[0] |
579 |
1 |
|
|
T1 |
3 |
|
T4 |
1 |
|
T10 |
1 |
zero_val |
higher_val |
auto[1] |
120 |
1 |
|
|
T1 |
2 |
|
T3 |
2 |
|
T4 |
2 |
zero_val |
lower_val |
auto[0] |
603 |
1 |
|
|
T1 |
4 |
|
T4 |
1 |
|
T31 |
3 |
zero_val |
lower_val |
auto[1] |
153 |
1 |
|
|
T4 |
1 |
|
T30 |
2 |
|
T33 |
2 |
zero_val |
zero_val |
auto[0] |
263 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T30 |
1 |
zero_val |
zero_val |
auto[1] |
178 |
1 |
|
|
T4 |
1 |
|
T30 |
1 |
|
T87 |
4 |