Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

Group : kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

---

Summary for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hash_mode	3	0	3	100.00	100	1	1	0
kmac_mode	2	0	2	100.00	100	1	1	2
msgfifo_depth	11	0	11	100.00	100	1	1	0
msgfifo_empty	2	0	2	100.00	100	1	1	2
msgfifo_full	2	0	2	100.00	100	1	1	2

Summary for Variable hash_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for hash_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
cshake	15613053	1			T1	193884		T4	5482		T10	9062
shake	57381820	1			T1	59732		T4	4826		T30	572250
sha3	35523335	1			T1	9729		T3	161453		T4	403

---

Summary for Variable kmac_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_mode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

92904023

1

T1

69450

T3

161453

T4

5228

auto[1]

15614185

1

T1

193895

T4

5483

T10

9062

---

Summary for Variable msgfifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for msgfifo_depth

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
depth[0x00]	92428841	1			T1	256001		T3	155849		T4	10131
depth[0x01]	3696076	1			T1	3278		T3	5580		T4	374
depth[0x02]	3230872	1			T1	1895		T3	24		T4	150
depth[0x03]	3014168	1			T1	1277		T4	52		T30	26684
depth[0x04]	2690156	1			T1	590		T4	4		T30	22535
depth[0x05]	1495998	1			T1	145		T30	9822		T10	189
depth[0x06]	395915	1			T1	11		T30	1		T10	61
depth[0x07]	322644	1			T1	7		T10	65		T33	12734
depth[0x08]	317530	1			T1	4		T10	74		T33	12705
depth[0x09]	298207	1			T1	32		T10	70		T33	12026
depth[0x0a]	627801	1			T1	105		T10	411		T33	19105

---

Summary for Variable msgfifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msgfifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16089367

1

T1

7344

T3

5604

T4

580

auto[1]

92428841

1

T1

256001

T3

155849

T4

10131

---

Summary for Variable msgfifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msgfifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

107890407

1

T1

263240

T3

161453

T4

10711

auto[1]

627801

1

T1

105

T10

411

T33

19105