Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100518776	1			T1	242269		T3	162074		T4	8360
all_pins[1]	100518776	1			T1	242269		T3	162074		T4	8360
all_pins[2]	100518776	1			T1	242269		T3	162074		T4	8360

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	249685216	1			T1	617628		T3	413352		T4	18431
values[0x1]	51871112	1			T1	109179		T3	72870		T4	6649
transitions[0x0=>0x1]	51443176	1			T1	106938		T3	72461		T4	5098
transitions[0x1=>0x0]	51443202	1			T1	106938		T3	72461		T4	5098

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100007602	1			T1	241614		T3	161607		T4	8155
all_pins[0]	values[0x1]	511174	1			T1	655		T3	467		T4	205
all_pins[0]	transitions[0x0=>0x1]	216483	1			T1	74		T3	58		T4	20
all_pins[0]	transitions[0x1=>0x0]	50733354	1			T1	104084		T3	71994		T4	3149
all_pins[1]	values[0x0]	49490731	1			T1	137604		T3	89671		T4	5026
all_pins[1]	values[0x1]	51028045	1			T1	104665		T3	72403		T4	3334
all_pins[1]	transitions[0x0=>0x1]	50896868	1			T1	103030		T3	72403		T4	1991
all_pins[1]	transitions[0x1=>0x0]	200716	1			T1	2224		T4	1767		T10	104
all_pins[2]	values[0x0]	100186883	1			T1	238410		T3	162074		T4	5250
all_pins[2]	values[0x1]	331893	1			T1	3859		T4	3110		T10	106
all_pins[2]	transitions[0x0=>0x1]	329825	1			T1	3834		T4	3087		T10	106
all_pins[2]	transitions[0x1=>0x0]	509132	1			T1	630		T3	467		T4	182