Summary for Variable in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for in_app_keymgr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
343290 |
1 |
|
|
T1 |
510 |
|
T3 |
298 |
|
T4 |
173 |
auto[1] |
3476 |
1 |
|
|
T1 |
25 |
|
T2 |
1 |
|
T4 |
8 |
Summary for Variable kmac_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
307711 |
1 |
|
|
T1 |
167 |
|
T3 |
298 |
|
T4 |
64 |
auto[1] |
39055 |
1 |
|
|
T1 |
368 |
|
T2 |
1 |
|
T4 |
117 |
Summary for Variable sideload
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sideload
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
332023 |
1 |
|
|
T1 |
450 |
|
T3 |
298 |
|
T4 |
151 |
auto[1] |
14743 |
1 |
|
|
T1 |
85 |
|
T2 |
1 |
|
T4 |
30 |
Summary for Cross sideload_cross
Samples crossed: sideload kmac_mode in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins for sideload_cross
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sw_kmac_valid_sideload |
14743 |
1 |
|
|
T1 |
85 |
|
T2 |
1 |
|
T4 |
30 |
sw_kmac_invalid_sideload |
332023 |
1 |
|
|
T1 |
450 |
|
T3 |
298 |
|
T4 |
151 |
app_valid_sideload |
14743 |
1 |
|
|
T1 |
85 |
|
T2 |
1 |
|
T4 |
30 |
app_invalid_sideload |
332023 |
1 |
|
|
T1 |
450 |
|
T3 |
298 |
|
T4 |
151 |