Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10864633 |
1 |
|
|
T1 |
61018 |
|
T3 |
3720 |
|
T4 |
11903 |
auto[1] |
10864608 |
1 |
|
|
T1 |
61018 |
|
T3 |
3720 |
|
T4 |
11903 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21488359 |
1 |
|
|
T1 |
121398 |
|
T3 |
7440 |
|
T4 |
23638 |
triple_byte_access |
80090 |
1 |
|
|
T1 |
208 |
|
T4 |
54 |
|
T30 |
558 |
halfword_access |
80496 |
1 |
|
|
T1 |
218 |
|
T4 |
50 |
|
T30 |
558 |
byte_access |
80296 |
1 |
|
|
T1 |
212 |
|
T4 |
64 |
|
T30 |
558 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10744192 |
1 |
|
|
T1 |
60699 |
|
T3 |
3720 |
|
T4 |
11819 |
auto[0] |
triple_byte_access |
40045 |
1 |
|
|
T1 |
104 |
|
T4 |
27 |
|
T30 |
279 |
auto[0] |
halfword_access |
40248 |
1 |
|
|
T1 |
109 |
|
T4 |
25 |
|
T30 |
279 |
auto[0] |
byte_access |
40148 |
1 |
|
|
T1 |
106 |
|
T4 |
32 |
|
T30 |
279 |
auto[1] |
word_access |
10744167 |
1 |
|
|
T1 |
60699 |
|
T3 |
3720 |
|
T4 |
11819 |
auto[1] |
triple_byte_access |
40045 |
1 |
|
|
T1 |
104 |
|
T4 |
27 |
|
T30 |
279 |
auto[1] |
halfword_access |
40248 |
1 |
|
|
T1 |
109 |
|
T4 |
25 |
|
T30 |
279 |
auto[1] |
byte_access |
40148 |
1 |
|
|
T1 |
106 |
|
T4 |
32 |
|
T30 |
279 |