Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 281 1 T119 4 T120 4 T121 7
all_values[1] 281 1 T119 4 T120 4 T121 7
all_values[2] 281 1 T119 4 T120 4 T121 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 460 1 T119 8 T120 3 T121 8
auto[1] 383 1 T119 4 T120 9 T121 13


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 353 1 T119 4 T120 5 T121 6
auto[1] 490 1 T119 8 T120 7 T121 15


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 502 1 T119 6 T120 6 T121 11
auto[1] 341 1 T119 6 T120 6 T121 10


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 60 1 T183 2 T165 1 T184 1
all_values[0] auto[0] auto[0] auto[1] 30 1 T121 1 T183 1 T185 1
all_values[0] auto[0] auto[1] auto[0] 47 1 T119 2 T120 2 T121 1
all_values[0] auto[0] auto[1] auto[1] 24 1 T121 2 T165 2 T184 1
all_values[0] auto[1] auto[0] auto[1] 69 1 T119 1 T121 3 T183 3
all_values[0] auto[1] auto[1] auto[1] 51 1 T119 1 T120 2 T183 1
all_values[1] auto[0] auto[0] auto[0] 70 1 T121 2 T183 2 T185 1
all_values[1] auto[0] auto[0] auto[1] 17 1 T119 1 T165 2 T184 1
all_values[1] auto[0] auto[1] auto[0] 62 1 T120 1 T121 1 T183 3
all_values[1] auto[0] auto[1] auto[1] 30 1 T120 1 T121 1 T165 1
all_values[1] auto[1] auto[0] auto[1] 60 1 T119 3 T121 1 T185 1
all_values[1] auto[1] auto[1] auto[1] 42 1 T120 2 T121 2 T183 2
all_values[2] auto[0] auto[0] auto[0] 71 1 T119 1 T120 2 T183 4
all_values[2] auto[0] auto[0] auto[1] 23 1 T119 1 T183 1 T184 1
all_values[2] auto[0] auto[1] auto[0] 43 1 T119 1 T121 2 T185 1
all_values[2] auto[0] auto[1] auto[1] 25 1 T121 1 T185 1 T165 1
all_values[2] auto[1] auto[0] auto[1] 60 1 T119 1 T120 1 T121 1
all_values[2] auto[1] auto[1] auto[1] 59 1 T120 1 T121 3 T185 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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