Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.96 98.38 93.14 99.69 94.55 96.04 98.89 98.03


Total test records in report: 1245
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T1044 /workspace/coverage/default/5.kmac_error.2384009244 Feb 25 01:55:58 PM PST 24 Feb 25 02:02:58 PM PST 24 13413091507 ps
T1045 /workspace/coverage/default/34.kmac_test_vectors_sha3_384.2139225295 Feb 25 02:00:31 PM PST 24 Feb 25 02:25:39 PM PST 24 19175051107 ps
T1046 /workspace/coverage/default/1.kmac_test_vectors_shake_128.661713339 Feb 25 01:55:18 PM PST 24 Feb 25 03:16:00 PM PST 24 63583738638 ps
T1047 /workspace/coverage/default/35.kmac_test_vectors_sha3_224.2052012809 Feb 25 02:00:41 PM PST 24 Feb 25 02:37:11 PM PST 24 40486473546 ps
T1048 /workspace/coverage/default/22.kmac_test_vectors_kmac.445487819 Feb 25 01:57:49 PM PST 24 Feb 25 01:57:56 PM PST 24 1114052122 ps
T1049 /workspace/coverage/default/38.kmac_test_vectors_shake_128.1118233669 Feb 25 02:01:40 PM PST 24 Feb 25 03:26:20 PM PST 24 129670738012 ps
T1050 /workspace/coverage/default/3.kmac_test_vectors_sha3_224.2071157737 Feb 25 01:55:30 PM PST 24 Feb 25 02:41:53 PM PST 24 691488713029 ps
T1051 /workspace/coverage/default/19.kmac_long_msg_and_output.1515052711 Feb 25 01:57:27 PM PST 24 Feb 25 02:35:55 PM PST 24 337709938983 ps
T1052 /workspace/coverage/default/13.kmac_test_vectors_shake_128.3892823679 Feb 25 01:56:32 PM PST 24 Feb 25 03:22:07 PM PST 24 320249092710 ps
T1053 /workspace/coverage/default/41.kmac_stress_all.192970881 Feb 25 02:02:51 PM PST 24 Feb 25 02:32:14 PM PST 24 131040823164 ps
T1054 /workspace/coverage/default/15.kmac_key_error.2722100297 Feb 25 01:56:55 PM PST 24 Feb 25 01:56:58 PM PST 24 453189770 ps
T1055 /workspace/coverage/default/17.kmac_lc_escalation.2786404152 Feb 25 01:57:16 PM PST 24 Feb 25 01:57:17 PM PST 24 47789816 ps
T1056 /workspace/coverage/default/18.kmac_test_vectors_kmac_xof.926794078 Feb 25 01:57:11 PM PST 24 Feb 25 01:57:18 PM PST 24 564427518 ps
T1057 /workspace/coverage/default/22.kmac_smoke.2524611026 Feb 25 01:57:48 PM PST 24 Feb 25 01:58:56 PM PST 24 5636330079 ps
T1058 /workspace/coverage/default/17.kmac_stress_all.3328373673 Feb 25 01:57:18 PM PST 24 Feb 25 02:18:04 PM PST 24 83395523394 ps
T1059 /workspace/coverage/default/25.kmac_key_error.2498238040 Feb 25 01:58:24 PM PST 24 Feb 25 01:58:31 PM PST 24 11086846364 ps
T1060 /workspace/coverage/default/39.kmac_burst_write.917668976 Feb 25 02:02:01 PM PST 24 Feb 25 02:16:54 PM PST 24 19243217878 ps
T1061 /workspace/coverage/default/19.kmac_entropy_refresh.1742774606 Feb 25 01:57:34 PM PST 24 Feb 25 02:03:33 PM PST 24 22128177793 ps
T1062 /workspace/coverage/default/4.kmac_test_vectors_sha3_256.1744371195 Feb 25 01:55:44 PM PST 24 Feb 25 02:33:20 PM PST 24 258177229462 ps
T1063 /workspace/coverage/default/9.kmac_app.2505719698 Feb 25 01:56:19 PM PST 24 Feb 25 01:56:38 PM PST 24 751778797 ps
T1064 /workspace/coverage/default/19.kmac_sideload.3465623228 Feb 25 01:57:27 PM PST 24 Feb 25 02:06:17 PM PST 24 15101884722 ps
T1065 /workspace/coverage/default/40.kmac_test_vectors_sha3_512.183023526 Feb 25 02:02:17 PM PST 24 Feb 25 02:19:00 PM PST 24 14335972710 ps
T1066 /workspace/coverage/default/27.kmac_alert_test.2128943083 Feb 25 01:58:58 PM PST 24 Feb 25 01:58:59 PM PST 24 78790993 ps
T1067 /workspace/coverage/default/28.kmac_test_vectors_sha3_256.3658371242 Feb 25 01:58:58 PM PST 24 Feb 25 02:35:30 PM PST 24 40158962762 ps
T1068 /workspace/coverage/default/9.kmac_test_vectors_sha3_512.1360452064 Feb 25 01:56:14 PM PST 24 Feb 25 02:16:15 PM PST 24 21619558824 ps
T1069 /workspace/coverage/default/9.kmac_test_vectors_kmac_xof.515853317 Feb 25 01:56:17 PM PST 24 Feb 25 01:56:24 PM PST 24 245606718 ps
T1070 /workspace/coverage/default/9.kmac_smoke.1750146077 Feb 25 01:56:13 PM PST 24 Feb 25 01:56:54 PM PST 24 6007905262 ps
T1071 /workspace/coverage/default/28.kmac_lc_escalation.3225288272 Feb 25 01:59:03 PM PST 24 Feb 25 01:59:04 PM PST 24 27584528 ps
T1072 /workspace/coverage/default/39.kmac_smoke.4116839816 Feb 25 02:01:58 PM PST 24 Feb 25 02:03:00 PM PST 24 1623730833 ps
T1073 /workspace/coverage/default/1.kmac_entropy_refresh.2654986087 Feb 25 01:55:30 PM PST 24 Feb 25 02:01:43 PM PST 24 31455700558 ps
T88 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1436894539 Feb 25 12:37:18 PM PST 24 Feb 25 12:37:19 PM PST 24 108618165 ps
T89 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.535295353 Feb 25 12:37:23 PM PST 24 Feb 25 12:37:26 PM PST 24 628342931 ps
T187 /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.1310677935 Feb 25 12:37:05 PM PST 24 Feb 25 12:37:07 PM PST 24 73773113 ps
T1074 /workspace/coverage/cover_reg_top/15.kmac_tl_errors.3393032118 Feb 25 12:37:22 PM PST 24 Feb 25 12:37:25 PM PST 24 45332204 ps
T90 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.2413692128 Feb 25 12:37:06 PM PST 24 Feb 25 12:37:07 PM PST 24 26562385 ps
T119 /workspace/coverage/cover_reg_top/13.kmac_intr_test.1362095487 Feb 25 12:37:15 PM PST 24 Feb 25 12:37:16 PM PST 24 31412143 ps
T120 /workspace/coverage/cover_reg_top/8.kmac_intr_test.2722748317 Feb 25 12:37:04 PM PST 24 Feb 25 12:37:04 PM PST 24 21437001 ps
T152 /workspace/coverage/cover_reg_top/11.kmac_csr_rw.928657700 Feb 25 12:37:03 PM PST 24 Feb 25 12:37:04 PM PST 24 34672234 ps
T121 /workspace/coverage/cover_reg_top/36.kmac_intr_test.2505096920 Feb 25 12:37:28 PM PST 24 Feb 25 12:37:29 PM PST 24 14950894 ps
T116 /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.374534537 Feb 25 12:37:10 PM PST 24 Feb 25 12:37:16 PM PST 24 443975190 ps
T97 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.1723829215 Feb 25 12:37:31 PM PST 24 Feb 25 12:37:34 PM PST 24 360708270 ps
T122 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.1567669463 Feb 25 12:37:13 PM PST 24 Feb 25 12:37:16 PM PST 24 374457249 ps
T1075 /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.4029344471 Feb 25 12:37:21 PM PST 24 Feb 25 12:37:24 PM PST 24 102049571 ps
T140 /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.2701879156 Feb 25 12:37:01 PM PST 24 Feb 25 12:37:02 PM PST 24 162878213 ps
T1076 /workspace/coverage/cover_reg_top/9.kmac_tl_errors.1488860326 Feb 25 12:37:19 PM PST 24 Feb 25 12:37:20 PM PST 24 20666578 ps
T91 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.520861121 Feb 25 12:37:15 PM PST 24 Feb 25 12:37:17 PM PST 24 145368173 ps
T92 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.1941169830 Feb 25 12:36:53 PM PST 24 Feb 25 12:36:56 PM PST 24 219051686 ps
T117 /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.1117235741 Feb 25 12:37:32 PM PST 24 Feb 25 12:37:37 PM PST 24 810188386 ps
T153 /workspace/coverage/cover_reg_top/19.kmac_csr_rw.342079412 Feb 25 12:37:12 PM PST 24 Feb 25 12:37:19 PM PST 24 29530259 ps
T1077 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.1304598316 Feb 25 12:36:56 PM PST 24 Feb 25 12:36:59 PM PST 24 173755205 ps
T1078 /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1780389273 Feb 25 12:37:30 PM PST 24 Feb 25 12:37:32 PM PST 24 256738329 ps
T1079 /workspace/coverage/cover_reg_top/7.kmac_csr_rw.1992906530 Feb 25 12:37:07 PM PST 24 Feb 25 12:37:09 PM PST 24 22490394 ps
T183 /workspace/coverage/cover_reg_top/32.kmac_intr_test.3736134393 Feb 25 12:37:16 PM PST 24 Feb 25 12:37:17 PM PST 24 25813414 ps
T185 /workspace/coverage/cover_reg_top/40.kmac_intr_test.3526111619 Feb 25 12:37:40 PM PST 24 Feb 25 12:37:41 PM PST 24 35148937 ps
T165 /workspace/coverage/cover_reg_top/25.kmac_intr_test.2791937760 Feb 25 12:37:39 PM PST 24 Feb 25 12:37:40 PM PST 24 58607602 ps
T1080 /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.3954339879 Feb 25 12:37:03 PM PST 24 Feb 25 12:37:05 PM PST 24 24938494 ps
T118 /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.3429393249 Feb 25 12:37:06 PM PST 24 Feb 25 12:37:10 PM PST 24 651749293 ps
T1081 /workspace/coverage/cover_reg_top/1.kmac_mem_walk.2833758497 Feb 25 12:36:48 PM PST 24 Feb 25 12:36:49 PM PST 24 32644179 ps
T166 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.2411188373 Feb 25 12:37:05 PM PST 24 Feb 25 12:37:07 PM PST 24 217194496 ps
T154 /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.642250759 Feb 25 12:37:10 PM PST 24 Feb 25 12:37:14 PM PST 24 451859821 ps
T184 /workspace/coverage/cover_reg_top/20.kmac_intr_test.1701539543 Feb 25 12:37:24 PM PST 24 Feb 25 12:37:25 PM PST 24 14950599 ps
T1082 /workspace/coverage/cover_reg_top/18.kmac_intr_test.832095574 Feb 25 12:37:12 PM PST 24 Feb 25 12:37:13 PM PST 24 26888474 ps
T115 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.179821194 Feb 25 12:37:00 PM PST 24 Feb 25 12:37:02 PM PST 24 337989059 ps
T1083 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2841698545 Feb 25 12:37:23 PM PST 24 Feb 25 12:37:25 PM PST 24 119046876 ps
T1084 /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.3217127236 Feb 25 12:37:17 PM PST 24 Feb 25 12:37:22 PM PST 24 167158813 ps
T155 /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.1514853919 Feb 25 12:37:08 PM PST 24 Feb 25 12:37:09 PM PST 24 39508642 ps
T1085 /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.1257435532 Feb 25 12:37:00 PM PST 24 Feb 25 12:37:01 PM PST 24 201350596 ps
T1086 /workspace/coverage/cover_reg_top/5.kmac_csr_rw.768946659 Feb 25 12:37:12 PM PST 24 Feb 25 12:37:13 PM PST 24 42267235 ps
T95 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.458503750 Feb 25 12:37:12 PM PST 24 Feb 25 12:37:15 PM PST 24 264675179 ps
T1087 /workspace/coverage/cover_reg_top/2.kmac_csr_rw.1586845293 Feb 25 12:37:05 PM PST 24 Feb 25 12:37:07 PM PST 24 464389703 ps
T1088 /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.3155721564 Feb 25 12:36:57 PM PST 24 Feb 25 12:37:00 PM PST 24 117521001 ps
T1089 /workspace/coverage/cover_reg_top/4.kmac_mem_walk.3110291602 Feb 25 12:37:02 PM PST 24 Feb 25 12:37:08 PM PST 24 20847993 ps
T1090 /workspace/coverage/cover_reg_top/2.kmac_mem_walk.1808951647 Feb 25 12:37:14 PM PST 24 Feb 25 12:37:15 PM PST 24 14424935 ps
T1091 /workspace/coverage/cover_reg_top/11.kmac_tl_errors.1008844887 Feb 25 12:37:03 PM PST 24 Feb 25 12:37:05 PM PST 24 240310212 ps
T1092 /workspace/coverage/cover_reg_top/49.kmac_intr_test.3125733702 Feb 25 12:37:24 PM PST 24 Feb 25 12:37:25 PM PST 24 33245794 ps
T1093 /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.186601369 Feb 25 12:37:00 PM PST 24 Feb 25 12:37:02 PM PST 24 38224908 ps
T1094 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.241995919 Feb 25 12:37:18 PM PST 24 Feb 25 12:37:19 PM PST 24 95620309 ps
T1095 /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.1282732054 Feb 25 12:37:04 PM PST 24 Feb 25 12:37:25 PM PST 24 9440700237 ps
T181 /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.87072844 Feb 25 12:37:21 PM PST 24 Feb 25 12:37:23 PM PST 24 94398628 ps
T1096 /workspace/coverage/cover_reg_top/16.kmac_tl_errors.224216979 Feb 25 12:37:10 PM PST 24 Feb 25 12:37:13 PM PST 24 272013650 ps
T1097 /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.4039787131 Feb 25 12:37:03 PM PST 24 Feb 25 12:37:06 PM PST 24 100000675 ps
T1098 /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.4049247651 Feb 25 12:36:58 PM PST 24 Feb 25 12:37:00 PM PST 24 42388862 ps
T178 /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.2702819487 Feb 25 12:37:03 PM PST 24 Feb 25 12:37:06 PM PST 24 141180447 ps
T1099 /workspace/coverage/cover_reg_top/5.kmac_intr_test.677767367 Feb 25 12:37:03 PM PST 24 Feb 25 12:37:04 PM PST 24 44542125 ps
T1100 /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.1105041135 Feb 25 12:37:08 PM PST 24 Feb 25 12:37:10 PM PST 24 78273678 ps
T1101 /workspace/coverage/cover_reg_top/8.kmac_tl_errors.2892826895 Feb 25 12:37:16 PM PST 24 Feb 25 12:37:18 PM PST 24 42892611 ps
T1102 /workspace/coverage/cover_reg_top/4.kmac_intr_test.410252823 Feb 25 12:37:09 PM PST 24 Feb 25 12:37:11 PM PST 24 21437133 ps
T1103 /workspace/coverage/cover_reg_top/2.kmac_tl_errors.2387860171 Feb 25 12:37:02 PM PST 24 Feb 25 12:37:04 PM PST 24 59769898 ps
T1104 /workspace/coverage/cover_reg_top/48.kmac_intr_test.3260783524 Feb 25 12:37:21 PM PST 24 Feb 25 12:37:23 PM PST 24 37030933 ps
T1105 /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.2622849283 Feb 25 12:37:17 PM PST 24 Feb 25 12:37:20 PM PST 24 607372373 ps
T1106 /workspace/coverage/cover_reg_top/23.kmac_intr_test.1035265738 Feb 25 12:37:31 PM PST 24 Feb 25 12:37:32 PM PST 24 74779516 ps
T1107 /workspace/coverage/cover_reg_top/9.kmac_intr_test.1521661946 Feb 25 12:37:05 PM PST 24 Feb 25 12:37:06 PM PST 24 43338026 ps
T1108 /workspace/coverage/cover_reg_top/31.kmac_intr_test.1789335252 Feb 25 12:37:06 PM PST 24 Feb 25 12:37:07 PM PST 24 37578612 ps
T1109 /workspace/coverage/cover_reg_top/0.kmac_mem_walk.1165299072 Feb 25 12:37:04 PM PST 24 Feb 25 12:37:05 PM PST 24 32722050 ps
T1110 /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.937736892 Feb 25 12:37:04 PM PST 24 Feb 25 12:37:08 PM PST 24 2318704641 ps
T1111 /workspace/coverage/cover_reg_top/7.kmac_intr_test.1586030681 Feb 25 12:37:03 PM PST 24 Feb 25 12:37:04 PM PST 24 29229926 ps
T1112 /workspace/coverage/cover_reg_top/0.kmac_intr_test.2752256599 Feb 25 12:37:04 PM PST 24 Feb 25 12:37:05 PM PST 24 16209594 ps
T1113 /workspace/coverage/cover_reg_top/27.kmac_intr_test.2385346197 Feb 25 12:37:23 PM PST 24 Feb 25 12:37:24 PM PST 24 13822811 ps
T93 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.2627313212 Feb 25 12:37:02 PM PST 24 Feb 25 12:37:03 PM PST 24 36125350 ps
T94 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.2270170759 Feb 25 12:37:12 PM PST 24 Feb 25 12:37:14 PM PST 24 260604697 ps
T1114 /workspace/coverage/cover_reg_top/16.kmac_csr_rw.3219416987 Feb 25 12:37:09 PM PST 24 Feb 25 12:37:11 PM PST 24 27151624 ps
T1115 /workspace/coverage/cover_reg_top/13.kmac_tl_errors.3592785763 Feb 25 12:37:09 PM PST 24 Feb 25 12:37:12 PM PST 24 254348928 ps
T1116 /workspace/coverage/cover_reg_top/14.kmac_intr_test.3222631285 Feb 25 12:37:20 PM PST 24 Feb 25 12:37:21 PM PST 24 17804497 ps
T1117 /workspace/coverage/cover_reg_top/12.kmac_csr_rw.1249906383 Feb 25 12:37:16 PM PST 24 Feb 25 12:37:17 PM PST 24 38832706 ps
T1118 /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.633316309 Feb 25 12:36:59 PM PST 24 Feb 25 12:37:21 PM PST 24 2011408055 ps
T1119 /workspace/coverage/cover_reg_top/37.kmac_intr_test.3523672175 Feb 25 12:37:23 PM PST 24 Feb 25 12:37:24 PM PST 24 78329549 ps
T1120 /workspace/coverage/cover_reg_top/10.kmac_csr_rw.289807013 Feb 25 12:37:04 PM PST 24 Feb 25 12:37:05 PM PST 24 28115929 ps
T1121 /workspace/coverage/cover_reg_top/24.kmac_intr_test.1737516482 Feb 25 12:37:27 PM PST 24 Feb 25 12:37:28 PM PST 24 17117374 ps
T174 /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.1440186085 Feb 25 12:37:12 PM PST 24 Feb 25 12:37:17 PM PST 24 195134805 ps
T1122 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.3514096515 Feb 25 12:37:18 PM PST 24 Feb 25 12:37:19 PM PST 24 57782625 ps
T1123 /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.1154572446 Feb 25 12:37:10 PM PST 24 Feb 25 12:37:13 PM PST 24 123793264 ps
T1124 /workspace/coverage/cover_reg_top/0.kmac_csr_rw.1066418140 Feb 25 12:36:54 PM PST 24 Feb 25 12:36:55 PM PST 24 24998183 ps
T1125 /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.3855158111 Feb 25 12:37:01 PM PST 24 Feb 25 12:37:03 PM PST 24 265879109 ps
T182 /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.1577574834 Feb 25 12:37:21 PM PST 24 Feb 25 12:37:24 PM PST 24 581674077 ps
T1126 /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.2754838708 Feb 25 12:37:02 PM PST 24 Feb 25 12:37:06 PM PST 24 381722042 ps
T179 /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.60727178 Feb 25 12:37:09 PM PST 24 Feb 25 12:37:13 PM PST 24 745042043 ps
T1127 /workspace/coverage/cover_reg_top/19.kmac_intr_test.2060990865 Feb 25 12:37:23 PM PST 24 Feb 25 12:37:24 PM PST 24 46037455 ps
T176 /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.3335017153 Feb 25 12:37:18 PM PST 24 Feb 25 12:37:24 PM PST 24 240462841 ps
T96 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.3965114715 Feb 25 12:37:26 PM PST 24 Feb 25 12:37:30 PM PST 24 173868979 ps
T1128 /workspace/coverage/cover_reg_top/7.kmac_tl_errors.2507571988 Feb 25 12:37:06 PM PST 24 Feb 25 12:37:09 PM PST 24 555223641 ps
T1129 /workspace/coverage/cover_reg_top/3.kmac_csr_rw.4171733370 Feb 25 12:37:05 PM PST 24 Feb 25 12:37:06 PM PST 24 21547450 ps
T1130 /workspace/coverage/cover_reg_top/47.kmac_intr_test.2083949526 Feb 25 12:37:34 PM PST 24 Feb 25 12:37:35 PM PST 24 40825178 ps
T1131 /workspace/coverage/cover_reg_top/46.kmac_intr_test.4126882849 Feb 25 12:37:19 PM PST 24 Feb 25 12:37:20 PM PST 24 29229190 ps
T1132 /workspace/coverage/cover_reg_top/17.kmac_csr_rw.4240461475 Feb 25 12:37:18 PM PST 24 Feb 25 12:37:19 PM PST 24 17742535 ps
T1133 /workspace/coverage/cover_reg_top/21.kmac_intr_test.3289419317 Feb 25 12:37:29 PM PST 24 Feb 25 12:37:30 PM PST 24 15590625 ps
T1134 /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.382622916 Feb 25 12:37:00 PM PST 24 Feb 25 12:37:04 PM PST 24 108551620 ps
T177 /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.1165004965 Feb 25 12:37:15 PM PST 24 Feb 25 12:37:18 PM PST 24 505205505 ps
T1135 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2432829137 Feb 25 12:37:01 PM PST 24 Feb 25 12:37:02 PM PST 24 158604819 ps
T1136 /workspace/coverage/cover_reg_top/18.kmac_tl_errors.1657812183 Feb 25 12:37:29 PM PST 24 Feb 25 12:37:32 PM PST 24 154211093 ps
T1137 /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.677120575 Feb 25 12:37:13 PM PST 24 Feb 25 12:37:15 PM PST 24 169170614 ps
T1138 /workspace/coverage/cover_reg_top/22.kmac_intr_test.3696195574 Feb 25 12:37:28 PM PST 24 Feb 25 12:37:29 PM PST 24 43553810 ps
T1139 /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.3386232647 Feb 25 12:37:04 PM PST 24 Feb 25 12:37:05 PM PST 24 71166034 ps
T1140 /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2603878859 Feb 25 12:37:23 PM PST 24 Feb 25 12:37:26 PM PST 24 77800452 ps
T1141 /workspace/coverage/cover_reg_top/42.kmac_intr_test.1312791761 Feb 25 12:37:22 PM PST 24 Feb 25 12:37:23 PM PST 24 43361140 ps
T1142 /workspace/coverage/cover_reg_top/41.kmac_intr_test.3059655259 Feb 25 12:37:32 PM PST 24 Feb 25 12:37:32 PM PST 24 13708836 ps
T1143 /workspace/coverage/cover_reg_top/29.kmac_intr_test.1714872827 Feb 25 12:37:33 PM PST 24 Feb 25 12:37:34 PM PST 24 14981640 ps
T1144 /workspace/coverage/cover_reg_top/1.kmac_tl_errors.79720925 Feb 25 12:36:57 PM PST 24 Feb 25 12:36:59 PM PST 24 57512862 ps
T1145 /workspace/coverage/cover_reg_top/6.kmac_csr_rw.3964676760 Feb 25 12:37:24 PM PST 24 Feb 25 12:37:25 PM PST 24 256875743 ps
T1146 /workspace/coverage/cover_reg_top/34.kmac_intr_test.533715267 Feb 25 12:37:35 PM PST 24 Feb 25 12:37:36 PM PST 24 19403529 ps
T1147 /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.963999832 Feb 25 12:37:06 PM PST 24 Feb 25 12:37:08 PM PST 24 25998076 ps
T1148 /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.3698464435 Feb 25 12:37:17 PM PST 24 Feb 25 12:37:20 PM PST 24 72717317 ps
T186 /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.3693841849 Feb 25 12:36:54 PM PST 24 Feb 25 12:36:58 PM PST 24 205844658 ps
T1149 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.2720658419 Feb 25 12:36:59 PM PST 24 Feb 25 12:37:01 PM PST 24 80233863 ps
T1150 /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.826131572 Feb 25 12:37:28 PM PST 24 Feb 25 12:37:32 PM PST 24 304508423 ps
T1151 /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.1318832922 Feb 25 12:37:02 PM PST 24 Feb 25 12:37:19 PM PST 24 320596393 ps
T1152 /workspace/coverage/cover_reg_top/11.kmac_intr_test.27529228 Feb 25 12:37:27 PM PST 24 Feb 25 12:37:28 PM PST 24 43191242 ps
T1153 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.3628251363 Feb 25 12:36:56 PM PST 24 Feb 25 12:37:00 PM PST 24 123461446 ps
T1154 /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.2024349262 Feb 25 12:37:25 PM PST 24 Feb 25 12:37:27 PM PST 24 40196073 ps
T1155 /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.994304979 Feb 25 12:37:12 PM PST 24 Feb 25 12:37:17 PM PST 24 300686611 ps
T1156 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.1225617281 Feb 25 12:37:19 PM PST 24 Feb 25 12:37:22 PM PST 24 79177472 ps
T1157 /workspace/coverage/cover_reg_top/19.kmac_tl_errors.2116866430 Feb 25 12:37:15 PM PST 24 Feb 25 12:37:17 PM PST 24 32845367 ps
T1158 /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.302529650 Feb 25 12:37:04 PM PST 24 Feb 25 12:37:07 PM PST 24 1720370201 ps
T1159 /workspace/coverage/cover_reg_top/43.kmac_intr_test.1193666647 Feb 25 12:37:32 PM PST 24 Feb 25 12:37:33 PM PST 24 28432385 ps
T1160 /workspace/coverage/cover_reg_top/17.kmac_intr_test.1279289699 Feb 25 12:37:12 PM PST 24 Feb 25 12:37:13 PM PST 24 13278190 ps
T1161 /workspace/coverage/cover_reg_top/4.kmac_csr_rw.4193350523 Feb 25 12:36:58 PM PST 24 Feb 25 12:37:00 PM PST 24 25559445 ps
T1162 /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.1470655100 Feb 25 12:37:03 PM PST 24 Feb 25 12:37:05 PM PST 24 33631019 ps
T1163 /workspace/coverage/cover_reg_top/4.kmac_tl_errors.831165144 Feb 25 12:37:14 PM PST 24 Feb 25 12:37:18 PM PST 24 211471328 ps
T1164 /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.1920026470 Feb 25 12:36:59 PM PST 24 Feb 25 12:37:04 PM PST 24 214226621 ps
T1165 /workspace/coverage/cover_reg_top/1.kmac_intr_test.3677976946 Feb 25 12:36:55 PM PST 24 Feb 25 12:36:56 PM PST 24 17073189 ps
T1166 /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1487846889 Feb 25 12:37:14 PM PST 24 Feb 25 12:37:16 PM PST 24 22515862 ps
T1167 /workspace/coverage/cover_reg_top/30.kmac_intr_test.2744768568 Feb 25 12:37:39 PM PST 24 Feb 25 12:37:40 PM PST 24 15632811 ps
T1168 /workspace/coverage/cover_reg_top/14.kmac_tl_errors.2749884988 Feb 25 12:37:06 PM PST 24 Feb 25 12:37:08 PM PST 24 46305185 ps
T1169 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.3737727779 Feb 25 12:37:04 PM PST 24 Feb 25 12:37:04 PM PST 24 41500070 ps
T1170 /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.4043040752 Feb 25 12:37:03 PM PST 24 Feb 25 12:37:09 PM PST 24 1078887143 ps
T1171 /workspace/coverage/cover_reg_top/13.kmac_csr_rw.2791111571 Feb 25 12:37:02 PM PST 24 Feb 25 12:37:04 PM PST 24 21684253 ps
T1172 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.2039524524 Feb 25 12:37:15 PM PST 24 Feb 25 12:37:17 PM PST 24 53185286 ps
T1173 /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.2781354444 Feb 25 12:37:01 PM PST 24 Feb 25 12:37:03 PM PST 24 63519736 ps
T175 /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.653679747 Feb 25 12:37:02 PM PST 24 Feb 25 12:37:06 PM PST 24 1186651804 ps
T1174 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.80550220 Feb 25 12:37:16 PM PST 24 Feb 25 12:37:19 PM PST 24 97295349 ps
T1175 /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2064462925 Feb 25 12:37:23 PM PST 24 Feb 25 12:37:25 PM PST 24 37766526 ps
T1176 /workspace/coverage/cover_reg_top/0.kmac_tl_errors.947563073 Feb 25 12:37:08 PM PST 24 Feb 25 12:37:12 PM PST 24 70771331 ps
T1177 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.485942600 Feb 25 12:37:02 PM PST 24 Feb 25 12:37:05 PM PST 24 182713551 ps
T1178 /workspace/coverage/cover_reg_top/3.kmac_intr_test.16366522 Feb 25 12:36:54 PM PST 24 Feb 25 12:36:55 PM PST 24 58501358 ps
T1179 /workspace/coverage/cover_reg_top/12.kmac_intr_test.1731037067 Feb 25 12:37:19 PM PST 24 Feb 25 12:37:20 PM PST 24 10760676 ps
T1180 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.2839731017 Feb 25 12:37:12 PM PST 24 Feb 25 12:37:14 PM PST 24 257542172 ps
T1181 /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.177760561 Feb 25 12:37:13 PM PST 24 Feb 25 12:37:30 PM PST 24 335832938 ps
T1182 /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.1452577910 Feb 25 12:37:13 PM PST 24 Feb 25 12:37:15 PM PST 24 640079513 ps
T141 /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.1131077455 Feb 25 12:37:02 PM PST 24 Feb 25 12:37:04 PM PST 24 49943544 ps
T1183 /workspace/coverage/cover_reg_top/9.kmac_csr_rw.121734875 Feb 25 12:37:01 PM PST 24 Feb 25 12:37:03 PM PST 24 23358619 ps
T1184 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.1169812516 Feb 25 12:36:53 PM PST 24 Feb 25 12:36:55 PM PST 24 166807124 ps
T1185 /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.1693277091 Feb 25 12:37:17 PM PST 24 Feb 25 12:37:20 PM PST 24 45132650 ps
T1186 /workspace/coverage/cover_reg_top/6.kmac_tl_errors.2071693161 Feb 25 12:36:54 PM PST 24 Feb 25 12:36:56 PM PST 24 79253003 ps
T1187 /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.3705621319 Feb 25 12:37:26 PM PST 24 Feb 25 12:37:29 PM PST 24 49876656 ps
T1188 /workspace/coverage/cover_reg_top/15.kmac_intr_test.1169634409 Feb 25 12:37:07 PM PST 24 Feb 25 12:37:08 PM PST 24 128571667 ps
T1189 /workspace/coverage/cover_reg_top/14.kmac_csr_rw.2910915168 Feb 25 12:37:13 PM PST 24 Feb 25 12:37:14 PM PST 24 29498037 ps
T1190 /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.665554902 Feb 25 12:37:02 PM PST 24 Feb 25 12:37:12 PM PST 24 149811764 ps
T1191 /workspace/coverage/cover_reg_top/38.kmac_intr_test.1293355500 Feb 25 12:37:24 PM PST 24 Feb 25 12:37:25 PM PST 24 27724887 ps
T1192 /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.3057097678 Feb 25 12:37:02 PM PST 24 Feb 25 12:37:04 PM PST 24 49585894 ps
T1193 /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1247401517 Feb 25 12:37:18 PM PST 24 Feb 25 12:37:20 PM PST 24 38426159 ps
T1194 /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.4065979888 Feb 25 12:36:52 PM PST 24 Feb 25 12:36:54 PM PST 24 59705158 ps
T1195 /workspace/coverage/cover_reg_top/10.kmac_tl_errors.1943021943 Feb 25 12:37:09 PM PST 24 Feb 25 12:37:12 PM PST 24 49165190 ps
T1196 /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.2535618706 Feb 25 12:37:11 PM PST 24 Feb 25 12:37:15 PM PST 24 207874217 ps
T142 /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.3867476353 Feb 25 12:36:50 PM PST 24 Feb 25 12:36:56 PM PST 24 21526447 ps
T1197 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.3934384141 Feb 25 12:37:17 PM PST 24 Feb 25 12:37:19 PM PST 24 92021451 ps
T1198 /workspace/coverage/cover_reg_top/8.kmac_csr_rw.2036224525 Feb 25 12:37:02 PM PST 24 Feb 25 12:37:04 PM PST 24 14976299 ps
T1199 /workspace/coverage/cover_reg_top/10.kmac_intr_test.4062920204 Feb 25 12:37:06 PM PST 24 Feb 25 12:37:07 PM PST 24 46030986 ps
T1200 /workspace/coverage/cover_reg_top/35.kmac_intr_test.1946301728 Feb 25 12:37:21 PM PST 24 Feb 25 12:37:21 PM PST 24 17642193 ps
T1201 /workspace/coverage/cover_reg_top/12.kmac_tl_errors.2098639300 Feb 25 12:37:17 PM PST 24 Feb 25 12:37:20 PM PST 24 239349559 ps
T1202 /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.157116314 Feb 25 12:37:04 PM PST 24 Feb 25 12:37:05 PM PST 24 35706323 ps
T1203 /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.776470980 Feb 25 12:37:19 PM PST 24 Feb 25 12:37:21 PM PST 24 188638249 ps
T1204 /workspace/coverage/cover_reg_top/16.kmac_intr_test.977976756 Feb 25 12:37:10 PM PST 24 Feb 25 12:37:11 PM PST 24 18516930 ps
T143 /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.1387781275 Feb 25 12:37:04 PM PST 24 Feb 25 12:37:05 PM PST 24 46994673 ps
T1205 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.838348275 Feb 25 12:37:24 PM PST 24 Feb 25 12:37:25 PM PST 24 31132500 ps
T1206 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.3601762099 Feb 25 12:37:05 PM PST 24 Feb 25 12:37:07 PM PST 24 91833989 ps
T1207 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.3508617477 Feb 25 12:37:02 PM PST 24 Feb 25 12:37:03 PM PST 24 610741050 ps
T1208 /workspace/coverage/cover_reg_top/2.kmac_intr_test.2530083480 Feb 25 12:36:57 PM PST 24 Feb 25 12:36:58 PM PST 24 17189577 ps
T1209 /workspace/coverage/cover_reg_top/15.kmac_csr_rw.3006377627 Feb 25 12:37:06 PM PST 24 Feb 25 12:37:08 PM PST 24 22937314 ps
T1210 /workspace/coverage/cover_reg_top/3.kmac_tl_errors.3704920191 Feb 25 12:37:01 PM PST 24 Feb 25 12:37:04 PM PST 24 153984038 ps
T1211 /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.412950210 Feb 25 12:37:12 PM PST 24 Feb 25 12:37:15 PM PST 24 144838777 ps
T1212 /workspace/coverage/cover_reg_top/39.kmac_intr_test.1625521223 Feb 25 12:37:03 PM PST 24 Feb 25 12:37:04 PM PST 24 35262966 ps
T1213 /workspace/coverage/cover_reg_top/3.kmac_mem_walk.2468012048 Feb 25 12:36:57 PM PST 24 Feb 25 12:36:58 PM PST 24 36169476 ps
T1214 /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.3386085214 Feb 25 12:37:03 PM PST 24 Feb 25 12:37:08 PM PST 24 183552968 ps
T1215 /workspace/coverage/cover_reg_top/5.kmac_tl_errors.2351844609 Feb 25 12:37:15 PM PST 24 Feb 25 12:37:19 PM PST 24 127417442 ps
T1216 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.1936367768 Feb 25 12:37:10 PM PST 24 Feb 25 12:37:13 PM PST 24 207133271 ps
T1217 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.192781685 Feb 25 12:37:03 PM PST 24 Feb 25 12:37:06 PM PST 24 737441683 ps
T1218 /workspace/coverage/cover_reg_top/18.kmac_csr_rw.1614073761 Feb 25 12:37:13 PM PST 24 Feb 25 12:37:14 PM PST 24 15741317 ps
T1219 /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.347668102 Feb 25 12:37:50 PM PST 24 Feb 25 12:37:53 PM PST 24 247884619 ps
T1220 /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.1521446720 Feb 25 12:37:09 PM PST 24 Feb 25 12:37:12 PM PST 24 86149387 ps
T1221 /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.1421480857 Feb 25 12:36:59 PM PST 24 Feb 25 12:37:00 PM PST 24 51901453 ps
T1222 /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.3038402361 Feb 25 12:37:00 PM PST 24 Feb 25 12:37:03 PM PST 24 137440352 ps
T1223 /workspace/coverage/cover_reg_top/45.kmac_intr_test.1372079213 Feb 25 12:37:42 PM PST 24 Feb 25 12:37:43 PM PST 24 33181041 ps
T1224 /workspace/coverage/cover_reg_top/44.kmac_intr_test.3457853328 Feb 25 12:37:23 PM PST 24 Feb 25 12:37:24 PM PST 24 27559984 ps
T1225 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2767720199 Feb 25 12:37:17 PM PST 24 Feb 25 12:37:18 PM PST 24 50536607 ps
T1226 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.3495110102 Feb 25 12:37:37 PM PST 24 Feb 25 12:37:38 PM PST 24 51116402 ps
T1227 /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.1463077615 Feb 25 12:37:27 PM PST 24 Feb 25 12:37:29 PM PST 24 419986810 ps
T180 /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.3397541236 Feb 25 12:37:02 PM PST 24 Feb 25 12:37:05 PM PST 24 399037206 ps
T1228 /workspace/coverage/cover_reg_top/17.kmac_tl_errors.4137311072 Feb 25 12:37:03 PM PST 24 Feb 25 12:37:06 PM PST 24 241628450 ps
T1229 /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.866460792 Feb 25 12:37:01 PM PST 24 Feb 25 12:37:03 PM PST 24 54930492 ps
T1230 /workspace/coverage/cover_reg_top/33.kmac_intr_test.1142477202 Feb 25 12:37:16 PM PST 24 Feb 25 12:37:17 PM PST 24 16103687 ps
T1231 /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.322231846 Feb 25 12:37:19 PM PST 24 Feb 25 12:37:28 PM PST 24 640570752 ps
T1232 /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.3099448590 Feb 25 12:37:29 PM PST 24 Feb 25 12:37:32 PM PST 24 97441714 ps
T1233 /workspace/coverage/cover_reg_top/28.kmac_intr_test.125390611 Feb 25 12:37:19 PM PST 24 Feb 25 12:37:21 PM PST 24 24136510 ps
T144 /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.3945052295 Feb 25 12:37:10 PM PST 24 Feb 25 12:37:11 PM PST 24 44586084 ps
T1234 /workspace/coverage/cover_reg_top/6.kmac_intr_test.2038542009 Feb 25 12:37:05 PM PST 24 Feb 25 12:37:06 PM PST 24 14511995 ps
T1235 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.1405308339 Feb 25 12:37:05 PM PST 24 Feb 25 12:37:08 PM PST 24 282264479 ps
T1236 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.250158987 Feb 25 12:37:19 PM PST 24 Feb 25 12:37:20 PM PST 24 68237660 ps
T1237 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.620638856 Feb 25 12:36:57 PM PST 24 Feb 25 12:36:59 PM PST 24 116742863 ps
T1238 /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.3700956017 Feb 25 12:37:01 PM PST 24 Feb 25 12:37:12 PM PST 24 531842027 ps
T1239 /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.3382838267 Feb 25 12:37:01 PM PST 24 Feb 25 12:37:03 PM PST 24 206865037 ps
T1240 /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.3180245715 Feb 25 12:37:12 PM PST 24 Feb 25 12:37:15 PM PST 24 40302709 ps
T1241 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.1441123309 Feb 25 12:37:13 PM PST 24 Feb 25 12:37:15 PM PST 24 47737905 ps
T1242 /workspace/coverage/cover_reg_top/26.kmac_intr_test.3904309339 Feb 25 12:37:22 PM PST 24 Feb 25 12:37:23 PM PST 24 53090715 ps
T1243 /workspace/coverage/cover_reg_top/1.kmac_csr_rw.2858410709 Feb 25 12:37:19 PM PST 24 Feb 25 12:37:21 PM PST 24 79218542 ps
T1244 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.2339633913 Feb 25 12:37:06 PM PST 24 Feb 25 12:37:09 PM PST 24 444832898 ps
T1245 /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.3433480693 Feb 25 12:37:01 PM PST 24 Feb 25 12:37:12 PM PST 24 440821559 ps


Test location /workspace/coverage/default/27.kmac_stress_all.2259698461
Short name T1
Test name
Test status
Simulation time 134958547487 ps
CPU time 3500.59 seconds
Started Feb 25 01:58:57 PM PST 24
Finished Feb 25 02:57:18 PM PST 24
Peak memory 505164 kb
Host smart-08013465-434a-401d-bb84-e029efdd4465
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2259698461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.2259698461 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_stress_all/latest


Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.1941169830
Short name T92
Test name
Test status
Simulation time 219051686 ps
CPU time 2.97 seconds
Started Feb 25 12:36:53 PM PST 24
Finished Feb 25 12:36:56 PM PST 24
Peak memory 219932 kb
Host smart-580b4d1f-01e9-41fc-8bf5-9e4ea09460df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941169830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac
_shadow_reg_errors_with_csr_rw.1941169830 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/default/0.kmac_sec_cm.698983968
Short name T6
Test name
Test status
Simulation time 7290387529 ps
CPU time 60.16 seconds
Started Feb 25 01:55:11 PM PST 24
Finished Feb 25 01:56:12 PM PST 24
Peak memory 266768 kb
Host smart-bfc66604-aec1-4dbb-8919-76263eedd7f5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698983968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.698983968 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/0.kmac_sec_cm/latest


Test location /workspace/coverage/default/30.kmac_stress_all_with_rand_reset.483925759
Short name T123
Test name
Test status
Simulation time 52496272304 ps
CPU time 1154.21 seconds
Started Feb 25 01:59:37 PM PST 24
Finished Feb 25 02:18:51 PM PST 24
Peak memory 292672 kb
Host smart-d4139336-5dbe-4ef0-bb84-85b28e78103a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=483925759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all_with_rand_reset.483925759 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/24.kmac_key_error.1701479443
Short name T36
Test name
Test status
Simulation time 1778966291 ps
CPU time 5.86 seconds
Started Feb 25 01:58:31 PM PST 24
Finished Feb 25 01:58:38 PM PST 24
Peak memory 218352 kb
Host smart-771d7e4c-6660-4204-9c1f-41ee0d75a6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701479443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.1701479443 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_key_error/latest


Test location /workspace/coverage/default/31.kmac_lc_escalation.2670752827
Short name T21
Test name
Test status
Simulation time 44965288 ps
CPU time 1.63 seconds
Started Feb 25 01:59:46 PM PST 24
Finished Feb 25 01:59:48 PM PST 24
Peak memory 219408 kb
Host smart-ac4f7b14-c088-40f0-aff6-ccd9ad11af8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670752827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.2670752827 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/31.kmac_lc_escalation/latest


Test location /workspace/coverage/default/8.kmac_error.312557588
Short name T45
Test name
Test status
Simulation time 8946350101 ps
CPU time 408.35 seconds
Started Feb 25 01:56:10 PM PST 24
Finished Feb 25 02:02:58 PM PST 24
Peak memory 257252 kb
Host smart-52d37d6d-4606-4bd6-8134-ffc154c63959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312557588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.312557588 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_error/latest


Test location /workspace/coverage/default/1.kmac_lc_escalation.2587685158
Short name T24
Test name
Test status
Simulation time 80038442 ps
CPU time 1.27 seconds
Started Feb 25 01:55:17 PM PST 24
Finished Feb 25 01:55:18 PM PST 24
Peak memory 218340 kb
Host smart-56c0f460-cae6-4c8f-9dfc-8ae1dc849146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587685158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.2587685158 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/1.kmac_lc_escalation/latest


Test location /workspace/coverage/default/0.kmac_entropy_ready_error.151071162
Short name T37
Test name
Test status
Simulation time 2201080598 ps
CPU time 12.61 seconds
Started Feb 25 01:55:18 PM PST 24
Finished Feb 25 01:55:31 PM PST 24
Peak memory 218468 kb
Host smart-18c15693-842b-4849-a394-d2cad84bb911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151071162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.151071162 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_ready_error/latest


Test location /workspace/coverage/default/11.kmac_edn_timeout_error.3577719281
Short name T75
Test name
Test status
Simulation time 29723198 ps
CPU time 1.1 seconds
Started Feb 25 01:56:29 PM PST 24
Finished Feb 25 01:56:30 PM PST 24
Peak memory 218144 kb
Host smart-6d2de996-5ab8-4afb-b1d4-a02d73975feb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3577719281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.3577719281 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_edn_timeout_error/latest


Test location /workspace/coverage/cover_reg_top/25.kmac_intr_test.2791937760
Short name T165
Test name
Test status
Simulation time 58607602 ps
CPU time 0.81 seconds
Started Feb 25 12:37:39 PM PST 24
Finished Feb 25 12:37:40 PM PST 24
Peak memory 216680 kb
Host smart-aa86f49b-3404-455a-8b69-fad81cf65fce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791937760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.2791937760 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.374534537
Short name T116
Test name
Test status
Simulation time 443975190 ps
CPU time 5.13 seconds
Started Feb 25 12:37:10 PM PST 24
Finished Feb 25 12:37:16 PM PST 24
Peak memory 216364 kb
Host smart-b49be4a7-bb3e-4f86-85ff-89d2786882e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374534537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.374534
537 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_tl_intg_err/latest


Test location /workspace/coverage/default/18.kmac_lc_escalation.1646087376
Short name T51
Test name
Test status
Simulation time 1628300873 ps
CPU time 10.98 seconds
Started Feb 25 01:57:27 PM PST 24
Finished Feb 25 01:57:38 PM PST 24
Peak memory 232768 kb
Host smart-85d98dc5-d648-4bfd-99d8-d315aee1a485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646087376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.1646087376 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/18.kmac_lc_escalation/latest


Test location /workspace/coverage/default/6.kmac_lc_escalation.2581930679
Short name T85
Test name
Test status
Simulation time 85397525 ps
CPU time 1.38 seconds
Started Feb 25 01:55:51 PM PST 24
Finished Feb 25 01:55:53 PM PST 24
Peak memory 219284 kb
Host smart-8f71837e-d35c-41f7-a82e-8a295e1392d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581930679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.2581930679 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/6.kmac_lc_escalation/latest


Test location /workspace/coverage/default/22.kmac_stress_all.4075838974
Short name T5
Test name
Test status
Simulation time 21325488433 ps
CPU time 629.01 seconds
Started Feb 25 01:58:00 PM PST 24
Finished Feb 25 02:08:30 PM PST 24
Peak memory 292100 kb
Host smart-c2b6d8ba-7bfe-48cb-ad8a-f117b469bbd1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4075838974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.4075838974 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_stress_all/latest


Test location /workspace/coverage/default/10.kmac_entropy_mode_error.3095238189
Short name T83
Test name
Test status
Simulation time 35515439 ps
CPU time 1.12 seconds
Started Feb 25 01:56:14 PM PST 24
Finished Feb 25 01:56:15 PM PST 24
Peak memory 218368 kb
Host smart-a9275fa3-0d56-4684-919b-d30989ea10d6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3095238189 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.3095238189 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/0.kmac_lc_escalation.3844846908
Short name T129
Test name
Test status
Simulation time 3600888593 ps
CPU time 37.72 seconds
Started Feb 25 01:55:10 PM PST 24
Finished Feb 25 01:55:49 PM PST 24
Peak memory 243092 kb
Host smart-8aa9e476-0cee-4b20-8470-ad387b501830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844846908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.3844846908 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/0.kmac_lc_escalation/latest


Test location /workspace/coverage/default/24.kmac_entropy_refresh.3998243473
Short name T27
Test name
Test status
Simulation time 15458751980 ps
CPU time 347.92 seconds
Started Feb 25 01:58:22 PM PST 24
Finished Feb 25 02:04:11 PM PST 24
Peak memory 250336 kb
Host smart-425f2039-e0ef-40ae-82f6-8389d76d4265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998243473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.3998243473 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/24.kmac_entropy_refresh/latest


Test location /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.3867476353
Short name T142
Test name
Test status
Simulation time 21526447 ps
CPU time 1.35 seconds
Started Feb 25 12:36:50 PM PST 24
Finished Feb 25 12:36:56 PM PST 24
Peak memory 217032 kb
Host smart-51fe36ee-ba0f-4ed6-bf11-eddf83d7786a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867476353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia
l_access.3867476353 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mem_partial_access/latest


Test location /workspace/coverage/default/11.kmac_lc_escalation.32183864
Short name T20
Test name
Test status
Simulation time 1168577607 ps
CPU time 14.53 seconds
Started Feb 25 01:56:25 PM PST 24
Finished Feb 25 01:56:39 PM PST 24
Peak memory 233548 kb
Host smart-286bccea-e6ce-4f31-a558-dbaa21cdeaf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32183864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.32183864 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_lc_escalation/latest


Test location /workspace/coverage/default/21.kmac_lc_escalation.2704242719
Short name T62
Test name
Test status
Simulation time 64484662 ps
CPU time 1.51 seconds
Started Feb 25 01:57:43 PM PST 24
Finished Feb 25 01:57:45 PM PST 24
Peak memory 219312 kb
Host smart-715f6eac-3288-45ea-9cdc-0cd0760cb5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704242719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.2704242719 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/21.kmac_lc_escalation/latest


Test location /workspace/coverage/default/12.kmac_alert_test.603446623
Short name T246
Test name
Test status
Simulation time 75243518 ps
CPU time 0.83 seconds
Started Feb 25 01:56:34 PM PST 24
Finished Feb 25 01:56:35 PM PST 24
Peak memory 219264 kb
Host smart-f73889b5-fe34-4f82-8e93-a605c6cadcac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603446623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.603446623 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/12.kmac_alert_test/latest


Test location /workspace/coverage/default/30.kmac_test_vectors_shake_256.1139704519
Short name T199
Test name
Test status
Simulation time 312978292243 ps
CPU time 5104.59 seconds
Started Feb 25 01:59:26 PM PST 24
Finished Feb 25 03:24:31 PM PST 24
Peak memory 584428 kb
Host smart-9b187fc2-5b93-42f9-9d70-4351c4d3420a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1139704519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_256.1139704519 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/cover_reg_top/32.kmac_intr_test.3736134393
Short name T183
Test name
Test status
Simulation time 25813414 ps
CPU time 0.8 seconds
Started Feb 25 12:37:16 PM PST 24
Finished Feb 25 12:37:17 PM PST 24
Peak memory 216868 kb
Host smart-ef06d249-e410-4c59-8899-2a2e70fa3b77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736134393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.3736134393 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_intr_test/latest


Test location /workspace/coverage/default/30.kmac_error.1765522339
Short name T424
Test name
Test status
Simulation time 4905320054 ps
CPU time 344.53 seconds
Started Feb 25 01:59:30 PM PST 24
Finished Feb 25 02:05:15 PM PST 24
Peak memory 259324 kb
Host smart-8d7f3d5f-00f0-4e76-9ff6-1f05664af27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765522339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.1765522339 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_error/latest


Test location /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.3335017153
Short name T176
Test name
Test status
Simulation time 240462841 ps
CPU time 5.39 seconds
Started Feb 25 12:37:18 PM PST 24
Finished Feb 25 12:37:24 PM PST 24
Peak memory 217020 kb
Host smart-27a6714f-b870-4f84-9db0-dbf3a6ceb484
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335017153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.3335
017153 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.2411188373
Short name T166
Test name
Test status
Simulation time 217194496 ps
CPU time 1.19 seconds
Started Feb 25 12:37:05 PM PST 24
Finished Feb 25 12:37:07 PM PST 24
Peak memory 217272 kb
Host smart-8dfc7476-b75d-41f2-a0c2-594cf5fe81ed
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411188373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg
_errors.2411188373 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.653679747
Short name T175
Test name
Test status
Simulation time 1186651804 ps
CPU time 3.37 seconds
Started Feb 25 12:37:02 PM PST 24
Finished Feb 25 12:37:06 PM PST 24
Peak memory 216884 kb
Host smart-f981c7b5-6d84-4894-80a4-5b5fb950742c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653679747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.653679
747 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_tl_intg_err/latest


Test location /workspace/coverage/default/20.kmac_stress_all.4162770327
Short name T43
Test name
Test status
Simulation time 157791453866 ps
CPU time 1493.87 seconds
Started Feb 25 01:57:32 PM PST 24
Finished Feb 25 02:22:26 PM PST 24
Peak memory 405112 kb
Host smart-575ace6c-5b4e-4599-bbb1-b810c58e3e48
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4162770327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.4162770327 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_stress_all/latest


Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.458503750
Short name T95
Test name
Test status
Simulation time 264675179 ps
CPU time 3.15 seconds
Started Feb 25 12:37:12 PM PST 24
Finished Feb 25 12:37:15 PM PST 24
Peak memory 224244 kb
Host smart-6da21558-9456-4179-ac25-9cbe356e0017
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458503750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_
shadow_reg_errors_with_csr_rw.458503750 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/default/0.kmac_test_vectors_shake_128.3783291425
Short name T34
Test name
Test status
Simulation time 121606523613 ps
CPU time 5391.55 seconds
Started Feb 25 01:55:20 PM PST 24
Finished Feb 25 03:25:12 PM PST 24
Peak memory 672488 kb
Host smart-bb69b8df-f17a-4f22-b316-f25e733b705c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3783291425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.3783291425 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/21.kmac_key_error.3034994950
Short name T41
Test name
Test status
Simulation time 1185075610 ps
CPU time 4.01 seconds
Started Feb 25 01:57:41 PM PST 24
Finished Feb 25 01:57:45 PM PST 24
Peak memory 218368 kb
Host smart-9ebf1b23-53c4-4f06-a509-bdf08f9b5052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034994950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.3034994950 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_key_error/latest


Test location /workspace/coverage/default/13.kmac_smoke.695934719
Short name T264
Test name
Test status
Simulation time 19396332882 ps
CPU time 91.51 seconds
Started Feb 25 01:56:31 PM PST 24
Finished Feb 25 01:58:05 PM PST 24
Peak memory 226712 kb
Host smart-3062c295-66dd-4405-b414-d21ae7522aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695934719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.695934719 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_smoke/latest


Test location /workspace/coverage/default/28.kmac_stress_all.1825729317
Short name T644
Test name
Test status
Simulation time 95986640836 ps
CPU time 2254.58 seconds
Started Feb 25 01:59:05 PM PST 24
Finished Feb 25 02:36:40 PM PST 24
Peak memory 432564 kb
Host smart-19546248-c1e8-4ef1-97c1-ead630396a77
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1825729317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.1825729317 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_stress_all/latest


Test location /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.3386085214
Short name T1214
Test name
Test status
Simulation time 183552968 ps
CPU time 4.98 seconds
Started Feb 25 12:37:03 PM PST 24
Finished Feb 25 12:37:08 PM PST 24
Peak memory 217028 kb
Host smart-71041121-2568-4f59-ae2f-4ad3e472bd01
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386085214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.3386085
214 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.1318832922
Short name T1151
Test name
Test status
Simulation time 320596393 ps
CPU time 17.06 seconds
Started Feb 25 12:37:02 PM PST 24
Finished Feb 25 12:37:19 PM PST 24
Peak memory 216192 kb
Host smart-68bb509d-43a6-4a91-85c5-2a87dc346e3a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318832922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.1318832
922 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.963999832
Short name T1147
Test name
Test status
Simulation time 25998076 ps
CPU time 1.01 seconds
Started Feb 25 12:37:06 PM PST 24
Finished Feb 25 12:37:08 PM PST 24
Peak memory 216120 kb
Host smart-c37b40b6-5fb7-4f3f-99fb-02ad71dc4574
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963999832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.96399983
2 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.1521446720
Short name T1220
Test name
Test status
Simulation time 86149387 ps
CPU time 1.72 seconds
Started Feb 25 12:37:09 PM PST 24
Finished Feb 25 12:37:12 PM PST 24
Peak memory 221224 kb
Host smart-125eb382-d20f-4213-892b-623f2d7e50c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521446720 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.1521446720 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/0.kmac_csr_rw.1066418140
Short name T1124
Test name
Test status
Simulation time 24998183 ps
CPU time 0.95 seconds
Started Feb 25 12:36:54 PM PST 24
Finished Feb 25 12:36:55 PM PST 24
Peak memory 216972 kb
Host smart-b9d42660-89ff-4757-8fec-c72fc4f81ced
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066418140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.1066418140 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/0.kmac_intr_test.2752256599
Short name T1112
Test name
Test status
Simulation time 16209594 ps
CPU time 0.79 seconds
Started Feb 25 12:37:04 PM PST 24
Finished Feb 25 12:37:05 PM PST 24
Peak memory 216840 kb
Host smart-4f7085e3-e3d5-4bd8-a75b-8e62ef434a7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752256599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.2752256599 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/0.kmac_mem_walk.1165299072
Short name T1109
Test name
Test status
Simulation time 32722050 ps
CPU time 0.76 seconds
Started Feb 25 12:37:04 PM PST 24
Finished Feb 25 12:37:05 PM PST 24
Peak memory 216872 kb
Host smart-9ead6c28-e3a6-4307-9fa1-16bf3ef162ff
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165299072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.1165299072
+enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.3155721564
Short name T1088
Test name
Test status
Simulation time 117521001 ps
CPU time 2.64 seconds
Started Feb 25 12:36:57 PM PST 24
Finished Feb 25 12:37:00 PM PST 24
Peak memory 216056 kb
Host smart-d535fc22-8cda-45d9-8e6e-f954d98c4c75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155721564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr
_outstanding.3155721564 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.1225617281
Short name T1156
Test name
Test status
Simulation time 79177472 ps
CPU time 1.65 seconds
Started Feb 25 12:37:19 PM PST 24
Finished Feb 25 12:37:22 PM PST 24
Peak memory 224424 kb
Host smart-a4bf9fa9-a2ff-45d6-86f3-b30f08873153
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225617281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_
errors.1225617281 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.1304598316
Short name T1077
Test name
Test status
Simulation time 173755205 ps
CPU time 1.7 seconds
Started Feb 25 12:36:56 PM PST 24
Finished Feb 25 12:36:59 PM PST 24
Peak memory 216272 kb
Host smart-6b76c413-bee0-47e6-9877-babeac7bb560
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304598316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac
_shadow_reg_errors_with_csr_rw.1304598316 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/0.kmac_tl_errors.947563073
Short name T1176
Test name
Test status
Simulation time 70771331 ps
CPU time 2.16 seconds
Started Feb 25 12:37:08 PM PST 24
Finished Feb 25 12:37:12 PM PST 24
Peak memory 217284 kb
Host smart-589e622b-73d0-417a-b35d-41927514ed01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947563073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.947563073 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/0.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.60727178
Short name T179
Test name
Test status
Simulation time 745042043 ps
CPU time 4.33 seconds
Started Feb 25 12:37:09 PM PST 24
Finished Feb 25 12:37:13 PM PST 24
Peak memory 216964 kb
Host smart-87fa95a3-b14f-46d0-af03-23ed452e7d46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60727178 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.6072717
8 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.3433480693
Short name T1245
Test name
Test status
Simulation time 440821559 ps
CPU time 11.33 seconds
Started Feb 25 12:37:01 PM PST 24
Finished Feb 25 12:37:12 PM PST 24
Peak memory 216180 kb
Host smart-444bf53b-7a09-46d6-b9f2-a3be8690d8ab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433480693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.3433480
693 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.633316309
Short name T1118
Test name
Test status
Simulation time 2011408055 ps
CPU time 21.77 seconds
Started Feb 25 12:36:59 PM PST 24
Finished Feb 25 12:37:21 PM PST 24
Peak memory 217008 kb
Host smart-2efb896a-adbb-4031-8ac4-9a8c0b9f9b2b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633316309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.63331630
9 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.2781354444
Short name T1173
Test name
Test status
Simulation time 63519736 ps
CPU time 1.18 seconds
Started Feb 25 12:37:01 PM PST 24
Finished Feb 25 12:37:03 PM PST 24
Peak memory 217032 kb
Host smart-c7687e67-5815-477c-9d29-656ce7a4330c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781354444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.2781354
444 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.186601369
Short name T1093
Test name
Test status
Simulation time 38224908 ps
CPU time 2.17 seconds
Started Feb 25 12:37:00 PM PST 24
Finished Feb 25 12:37:02 PM PST 24
Peak memory 221900 kb
Host smart-5ed99f54-6747-4de0-b706-4f6c16b2deb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186601369 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.186601369 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/1.kmac_csr_rw.2858410709
Short name T1243
Test name
Test status
Simulation time 79218542 ps
CPU time 1.03 seconds
Started Feb 25 12:37:19 PM PST 24
Finished Feb 25 12:37:21 PM PST 24
Peak memory 220908 kb
Host smart-cc812613-60f9-4b6a-9a77-ba52c3d87994
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858410709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.2858410709 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/1.kmac_intr_test.3677976946
Short name T1165
Test name
Test status
Simulation time 17073189 ps
CPU time 0.82 seconds
Started Feb 25 12:36:55 PM PST 24
Finished Feb 25 12:36:56 PM PST 24
Peak memory 216804 kb
Host smart-76338af8-630f-4582-a8eb-06923416c45b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677976946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.3677976946 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.2701879156
Short name T140
Test name
Test status
Simulation time 162878213 ps
CPU time 1.12 seconds
Started Feb 25 12:37:01 PM PST 24
Finished Feb 25 12:37:02 PM PST 24
Peak memory 216932 kb
Host smart-7f2967a5-07b0-4c31-aef4-9833b7c55b45
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701879156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partia
l_access.2701879156 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/1.kmac_mem_walk.2833758497
Short name T1081
Test name
Test status
Simulation time 32644179 ps
CPU time 0.75 seconds
Started Feb 25 12:36:48 PM PST 24
Finished Feb 25 12:36:49 PM PST 24
Peak memory 216704 kb
Host smart-64527bd2-dc4f-4fec-b9f9-b14ce875ff7c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833758497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.2833758497
+enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.2622849283
Short name T1105
Test name
Test status
Simulation time 607372373 ps
CPU time 2.7 seconds
Started Feb 25 12:37:17 PM PST 24
Finished Feb 25 12:37:20 PM PST 24
Peak memory 216112 kb
Host smart-b52704f6-5a64-4c7d-867a-9c654885886b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622849283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr
_outstanding.2622849283 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.2627313212
Short name T93
Test name
Test status
Simulation time 36125350 ps
CPU time 1.14 seconds
Started Feb 25 12:37:02 PM PST 24
Finished Feb 25 12:37:03 PM PST 24
Peak memory 221012 kb
Host smart-badfff62-5e9b-4db9-80ed-d0d0a3a13641
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627313212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_
errors.2627313212 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/1.kmac_tl_errors.79720925
Short name T1144
Test name
Test status
Simulation time 57512862 ps
CPU time 1.7 seconds
Started Feb 25 12:36:57 PM PST 24
Finished Feb 25 12:36:59 PM PST 24
Peak memory 217172 kb
Host smart-681032e9-9ffd-4d92-8455-87ab83db6358
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79720925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.79720925 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/1.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.3693841849
Short name T186
Test name
Test status
Simulation time 205844658 ps
CPU time 3.11 seconds
Started Feb 25 12:36:54 PM PST 24
Finished Feb 25 12:36:58 PM PST 24
Peak memory 216960 kb
Host smart-41830948-a3f8-437c-a9dd-05ded920d0e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693841849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.36938
41849 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.3180245715
Short name T1240
Test name
Test status
Simulation time 40302709 ps
CPU time 1.61 seconds
Started Feb 25 12:37:12 PM PST 24
Finished Feb 25 12:37:15 PM PST 24
Peak memory 220404 kb
Host smart-1876ee75-f0ad-4f86-bcb4-2902989bd4c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180245715 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.3180245715 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/10.kmac_csr_rw.289807013
Short name T1120
Test name
Test status
Simulation time 28115929 ps
CPU time 1.1 seconds
Started Feb 25 12:37:04 PM PST 24
Finished Feb 25 12:37:05 PM PST 24
Peak memory 217040 kb
Host smart-c811e8a5-e2f3-454a-89a1-c9950b9d03af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289807013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.289807013 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/10.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/10.kmac_intr_test.4062920204
Short name T1199
Test name
Test status
Simulation time 46030986 ps
CPU time 0.85 seconds
Started Feb 25 12:37:06 PM PST 24
Finished Feb 25 12:37:07 PM PST 24
Peak memory 216952 kb
Host smart-d54b2579-afb2-416b-a7a4-7371c06d5feb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062920204 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.4062920204 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.866460792
Short name T1229
Test name
Test status
Simulation time 54930492 ps
CPU time 1.81 seconds
Started Feb 25 12:37:01 PM PST 24
Finished Feb 25 12:37:03 PM PST 24
Peak memory 216984 kb
Host smart-335ada62-a4d2-43cd-b236-8f27fec08ee8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866460792 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_csr
_outstanding.866460792 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.3508617477
Short name T1207
Test name
Test status
Simulation time 610741050 ps
CPU time 1.28 seconds
Started Feb 25 12:37:02 PM PST 24
Finished Feb 25 12:37:03 PM PST 24
Peak memory 224380 kb
Host smart-abc50527-2d3d-4a32-ab93-cc6d3ddba149
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508617477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg
_errors.3508617477 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.485942600
Short name T1177
Test name
Test status
Simulation time 182713551 ps
CPU time 2.79 seconds
Started Feb 25 12:37:02 PM PST 24
Finished Feb 25 12:37:05 PM PST 24
Peak memory 220864 kb
Host smart-cfb304e1-6c00-4b4c-b94e-e5338973924e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485942600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac
_shadow_reg_errors_with_csr_rw.485942600 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/10.kmac_tl_errors.1943021943
Short name T1195
Test name
Test status
Simulation time 49165190 ps
CPU time 1.89 seconds
Started Feb 25 12:37:09 PM PST 24
Finished Feb 25 12:37:12 PM PST 24
Peak memory 217148 kb
Host smart-e0be8221-783c-426a-a353-ca858f4cab4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943021943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.1943021943 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.1165004965
Short name T177
Test name
Test status
Simulation time 505205505 ps
CPU time 3.26 seconds
Started Feb 25 12:37:15 PM PST 24
Finished Feb 25 12:37:18 PM PST 24
Peak memory 217008 kb
Host smart-3c5cef6c-fa6f-46e8-ac82-135229f3e026
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165004965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.1165
004965 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.3954339879
Short name T1080
Test name
Test status
Simulation time 24938494 ps
CPU time 1.67 seconds
Started Feb 25 12:37:03 PM PST 24
Finished Feb 25 12:37:05 PM PST 24
Peak memory 222724 kb
Host smart-342b8f2d-2d87-4d5f-a819-4566df199299
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954339879 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.3954339879 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/11.kmac_csr_rw.928657700
Short name T152
Test name
Test status
Simulation time 34672234 ps
CPU time 1.25 seconds
Started Feb 25 12:37:03 PM PST 24
Finished Feb 25 12:37:04 PM PST 24
Peak memory 216980 kb
Host smart-45cf25e5-be1a-440e-9de6-0c3c45405c00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928657700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.928657700 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/11.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/11.kmac_intr_test.27529228
Short name T1152
Test name
Test status
Simulation time 43191242 ps
CPU time 0.8 seconds
Started Feb 25 12:37:27 PM PST 24
Finished Feb 25 12:37:28 PM PST 24
Peak memory 216084 kb
Host smart-8de43fc8-8800-454c-bfc1-49ee723c737c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27529228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.27529228 +enable_mas
king=1 +sw_key_masked=0
Directory /workspace/11.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.2024349262
Short name T1154
Test name
Test status
Simulation time 40196073 ps
CPU time 2.38 seconds
Started Feb 25 12:37:25 PM PST 24
Finished Feb 25 12:37:27 PM PST 24
Peak memory 216848 kb
Host smart-42f4cf22-d79c-4864-92fd-dd2fb1d375e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024349262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_cs
r_outstanding.2024349262 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.838348275
Short name T1205
Test name
Test status
Simulation time 31132500 ps
CPU time 1.18 seconds
Started Feb 25 12:37:24 PM PST 24
Finished Feb 25 12:37:25 PM PST 24
Peak memory 218184 kb
Host smart-0aae5528-20b8-43e7-a60a-1a9f4278f538
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838348275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_
errors.838348275 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.3601762099
Short name T1206
Test name
Test status
Simulation time 91833989 ps
CPU time 2.64 seconds
Started Feb 25 12:37:05 PM PST 24
Finished Feb 25 12:37:07 PM PST 24
Peak memory 220564 kb
Host smart-06e06999-abb0-426f-9ec0-ce3830e94f97
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601762099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kma
c_shadow_reg_errors_with_csr_rw.3601762099 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/11.kmac_tl_errors.1008844887
Short name T1091
Test name
Test status
Simulation time 240310212 ps
CPU time 1.99 seconds
Started Feb 25 12:37:03 PM PST 24
Finished Feb 25 12:37:05 PM PST 24
Peak memory 217296 kb
Host smart-29cb8b7f-d161-4203-bc6f-81210bec0963
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008844887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.1008844887 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.412950210
Short name T1211
Test name
Test status
Simulation time 144838777 ps
CPU time 2.97 seconds
Started Feb 25 12:37:12 PM PST 24
Finished Feb 25 12:37:15 PM PST 24
Peak memory 216976 kb
Host smart-6795478f-d55e-421a-8016-310aa80ac666
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412950210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.41295
0210 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1247401517
Short name T1193
Test name
Test status
Simulation time 38426159 ps
CPU time 1.57 seconds
Started Feb 25 12:37:18 PM PST 24
Finished Feb 25 12:37:20 PM PST 24
Peak memory 220980 kb
Host smart-899cc4af-202b-4692-98b4-33ccb53b0a49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247401517 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.1247401517 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/12.kmac_csr_rw.1249906383
Short name T1117
Test name
Test status
Simulation time 38832706 ps
CPU time 0.95 seconds
Started Feb 25 12:37:16 PM PST 24
Finished Feb 25 12:37:17 PM PST 24
Peak memory 216812 kb
Host smart-7a62cea1-72cc-41a9-b576-400dc09b3be2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249906383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.1249906383 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/12.kmac_intr_test.1731037067
Short name T1179
Test name
Test status
Simulation time 10760676 ps
CPU time 0.76 seconds
Started Feb 25 12:37:19 PM PST 24
Finished Feb 25 12:37:20 PM PST 24
Peak memory 216792 kb
Host smart-c21846f2-a1d1-4b54-8fd5-461a8ecef9bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731037067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.1731037067 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.347668102
Short name T1219
Test name
Test status
Simulation time 247884619 ps
CPU time 2.54 seconds
Started Feb 25 12:37:50 PM PST 24
Finished Feb 25 12:37:53 PM PST 24
Peak memory 216104 kb
Host smart-901e17d9-b3eb-4ffd-86d2-a2099065f87f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347668102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_csr
_outstanding.347668102 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2767720199
Short name T1225
Test name
Test status
Simulation time 50536607 ps
CPU time 0.95 seconds
Started Feb 25 12:37:17 PM PST 24
Finished Feb 25 12:37:18 PM PST 24
Peak memory 215976 kb
Host smart-7932faf8-4ff0-48ed-9296-be28f411e9b0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767720199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg
_errors.2767720199 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.2339633913
Short name T1244
Test name
Test status
Simulation time 444832898 ps
CPU time 3.2 seconds
Started Feb 25 12:37:06 PM PST 24
Finished Feb 25 12:37:09 PM PST 24
Peak memory 219820 kb
Host smart-d094a678-913d-4b02-bf87-4bceceeb1f40
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339633913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kma
c_shadow_reg_errors_with_csr_rw.2339633913 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/12.kmac_tl_errors.2098639300
Short name T1201
Test name
Test status
Simulation time 239349559 ps
CPU time 3.23 seconds
Started Feb 25 12:37:17 PM PST 24
Finished Feb 25 12:37:20 PM PST 24
Peak memory 217180 kb
Host smart-d18ec37d-30a1-4fdb-b4fb-aa8df22c5e5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098639300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.2098639300 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.1440186085
Short name T174
Test name
Test status
Simulation time 195134805 ps
CPU time 4.53 seconds
Started Feb 25 12:37:12 PM PST 24
Finished Feb 25 12:37:17 PM PST 24
Peak memory 217036 kb
Host smart-f0d3f92e-5afa-494f-8b96-b3c41eb97f73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440186085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.1440
186085 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.1310677935
Short name T187
Test name
Test status
Simulation time 73773113 ps
CPU time 1.61 seconds
Started Feb 25 12:37:05 PM PST 24
Finished Feb 25 12:37:07 PM PST 24
Peak memory 218760 kb
Host smart-353e626b-3500-4e81-ac36-cae29deb9659
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310677935 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.1310677935 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/13.kmac_csr_rw.2791111571
Short name T1171
Test name
Test status
Simulation time 21684253 ps
CPU time 1.02 seconds
Started Feb 25 12:37:02 PM PST 24
Finished Feb 25 12:37:04 PM PST 24
Peak memory 216100 kb
Host smart-3beb12c8-d185-43b0-a155-e095521ef3ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791111571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.2791111571 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/13.kmac_intr_test.1362095487
Short name T119
Test name
Test status
Simulation time 31412143 ps
CPU time 0.75 seconds
Started Feb 25 12:37:15 PM PST 24
Finished Feb 25 12:37:16 PM PST 24
Peak memory 216808 kb
Host smart-a3bc8db8-7260-412a-8c22-f9827613aa27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362095487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.1362095487 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.1154572446
Short name T1123
Test name
Test status
Simulation time 123793264 ps
CPU time 2.76 seconds
Started Feb 25 12:37:10 PM PST 24
Finished Feb 25 12:37:13 PM PST 24
Peak memory 217040 kb
Host smart-92dfc0a4-0984-42a0-ac80-d893ad9b1591
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154572446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_cs
r_outstanding.1154572446 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.3628251363
Short name T1153
Test name
Test status
Simulation time 123461446 ps
CPU time 1.95 seconds
Started Feb 25 12:36:56 PM PST 24
Finished Feb 25 12:37:00 PM PST 24
Peak memory 219812 kb
Host smart-66bc94b7-5ab2-4fe0-bd75-501bde0e29e8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628251363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kma
c_shadow_reg_errors_with_csr_rw.3628251363 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/13.kmac_tl_errors.3592785763
Short name T1115
Test name
Test status
Simulation time 254348928 ps
CPU time 1.81 seconds
Started Feb 25 12:37:09 PM PST 24
Finished Feb 25 12:37:12 PM PST 24
Peak memory 216260 kb
Host smart-594a4a53-207b-49cc-9877-7ad108a4c0a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592785763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.3592785763 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.3038402361
Short name T1222
Test name
Test status
Simulation time 137440352 ps
CPU time 2.72 seconds
Started Feb 25 12:37:00 PM PST 24
Finished Feb 25 12:37:03 PM PST 24
Peak memory 217012 kb
Host smart-c528f6f8-331c-4a19-80b3-88cf39a9f84a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038402361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.3038
402361 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.776470980
Short name T1203
Test name
Test status
Simulation time 188638249 ps
CPU time 1.96 seconds
Started Feb 25 12:37:19 PM PST 24
Finished Feb 25 12:37:21 PM PST 24
Peak memory 221332 kb
Host smart-b7c9d67e-f88a-4ba6-82ca-81762d7947dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776470980 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.776470980 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/14.kmac_csr_rw.2910915168
Short name T1189
Test name
Test status
Simulation time 29498037 ps
CPU time 1.15 seconds
Started Feb 25 12:37:13 PM PST 24
Finished Feb 25 12:37:14 PM PST 24
Peak memory 216864 kb
Host smart-bab94f46-dae8-4d40-a13a-5a3dc1d586a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910915168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.2910915168 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/14.kmac_intr_test.3222631285
Short name T1116
Test name
Test status
Simulation time 17804497 ps
CPU time 0.82 seconds
Started Feb 25 12:37:20 PM PST 24
Finished Feb 25 12:37:21 PM PST 24
Peak memory 216876 kb
Host smart-745d360a-3a47-4319-a6cf-240f280e8734
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222631285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.3222631285 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.3705621319
Short name T1187
Test name
Test status
Simulation time 49876656 ps
CPU time 1.53 seconds
Started Feb 25 12:37:26 PM PST 24
Finished Feb 25 12:37:29 PM PST 24
Peak memory 217016 kb
Host smart-a3f4c8bc-ac04-4023-b5f0-0d201697db9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705621319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_cs
r_outstanding.3705621319 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.3495110102
Short name T1226
Test name
Test status
Simulation time 51116402 ps
CPU time 1.45 seconds
Started Feb 25 12:37:37 PM PST 24
Finished Feb 25 12:37:38 PM PST 24
Peak memory 224432 kb
Host smart-f34d2452-d054-49e7-9dac-19ed8ae8a841
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495110102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg
_errors.3495110102 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.535295353
Short name T89
Test name
Test status
Simulation time 628342931 ps
CPU time 2.48 seconds
Started Feb 25 12:37:23 PM PST 24
Finished Feb 25 12:37:26 PM PST 24
Peak memory 219620 kb
Host smart-4cb0cf10-66a9-4257-b3c8-3eac6676a94f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535295353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac
_shadow_reg_errors_with_csr_rw.535295353 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/14.kmac_tl_errors.2749884988
Short name T1168
Test name
Test status
Simulation time 46305185 ps
CPU time 1.79 seconds
Started Feb 25 12:37:06 PM PST 24
Finished Feb 25 12:37:08 PM PST 24
Peak memory 216208 kb
Host smart-8f1d4674-6cc3-47fd-9c6c-edaf61e86c8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749884988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.2749884988 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.87072844
Short name T181
Test name
Test status
Simulation time 94398628 ps
CPU time 2.66 seconds
Started Feb 25 12:37:21 PM PST 24
Finished Feb 25 12:37:23 PM PST 24
Peak memory 216968 kb
Host smart-91831eb8-61ab-4891-b4e5-6f9626c9496b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87072844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.870728
44 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1780389273
Short name T1078
Test name
Test status
Simulation time 256738329 ps
CPU time 1.89 seconds
Started Feb 25 12:37:30 PM PST 24
Finished Feb 25 12:37:32 PM PST 24
Peak memory 218696 kb
Host smart-306e2589-de04-428d-ba7c-61e540112f79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780389273 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.1780389273 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/15.kmac_csr_rw.3006377627
Short name T1209
Test name
Test status
Simulation time 22937314 ps
CPU time 1.06 seconds
Started Feb 25 12:37:06 PM PST 24
Finished Feb 25 12:37:08 PM PST 24
Peak memory 216076 kb
Host smart-22b7f05c-8e23-4e95-8c40-90d5cbf17fb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006377627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.3006377627 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/15.kmac_intr_test.1169634409
Short name T1188
Test name
Test status
Simulation time 128571667 ps
CPU time 0.79 seconds
Started Feb 25 12:37:07 PM PST 24
Finished Feb 25 12:37:08 PM PST 24
Peak memory 216964 kb
Host smart-6b5d7448-546e-4461-80b1-899962ef92d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169634409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.1169634409 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.4029344471
Short name T1075
Test name
Test status
Simulation time 102049571 ps
CPU time 1.68 seconds
Started Feb 25 12:37:21 PM PST 24
Finished Feb 25 12:37:24 PM PST 24
Peak memory 216812 kb
Host smart-0a641b3f-e434-4326-8f6f-389a2a88d932
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029344471 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_cs
r_outstanding.4029344471 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.3514096515
Short name T1122
Test name
Test status
Simulation time 57782625 ps
CPU time 0.9 seconds
Started Feb 25 12:37:18 PM PST 24
Finished Feb 25 12:37:19 PM PST 24
Peak memory 216064 kb
Host smart-a97fdef3-31b9-4ca1-adf5-55145a69bcad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514096515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg
_errors.3514096515 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.1936367768
Short name T1216
Test name
Test status
Simulation time 207133271 ps
CPU time 1.98 seconds
Started Feb 25 12:37:10 PM PST 24
Finished Feb 25 12:37:13 PM PST 24
Peak memory 224144 kb
Host smart-11ece105-19c2-412b-810b-2651d9189707
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936367768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kma
c_shadow_reg_errors_with_csr_rw.1936367768 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/15.kmac_tl_errors.3393032118
Short name T1074
Test name
Test status
Simulation time 45332204 ps
CPU time 2.69 seconds
Started Feb 25 12:37:22 PM PST 24
Finished Feb 25 12:37:25 PM PST 24
Peak memory 217204 kb
Host smart-35f325c0-0f08-49f0-8587-ca44ba6a85be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393032118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.3393032118 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.826131572
Short name T1150
Test name
Test status
Simulation time 304508423 ps
CPU time 4.24 seconds
Started Feb 25 12:37:28 PM PST 24
Finished Feb 25 12:37:32 PM PST 24
Peak memory 217108 kb
Host smart-208c718d-7894-4c73-8655-b53f881588a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826131572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.82613
1572 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.3099448590
Short name T1232
Test name
Test status
Simulation time 97441714 ps
CPU time 2.61 seconds
Started Feb 25 12:37:29 PM PST 24
Finished Feb 25 12:37:32 PM PST 24
Peak memory 222440 kb
Host smart-77f32594-9d08-4ea2-ac5b-1c376bc4540e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099448590 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.3099448590 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/16.kmac_csr_rw.3219416987
Short name T1114
Test name
Test status
Simulation time 27151624 ps
CPU time 1.14 seconds
Started Feb 25 12:37:09 PM PST 24
Finished Feb 25 12:37:11 PM PST 24
Peak memory 217024 kb
Host smart-f469496d-73c3-4d78-91f6-8b526bb0a17c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219416987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.3219416987 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/16.kmac_intr_test.977976756
Short name T1204
Test name
Test status
Simulation time 18516930 ps
CPU time 0.78 seconds
Started Feb 25 12:37:10 PM PST 24
Finished Feb 25 12:37:11 PM PST 24
Peak memory 215892 kb
Host smart-5d11b617-7487-42e9-a8e1-20c516782b4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977976756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.977976756 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/16.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.642250759
Short name T154
Test name
Test status
Simulation time 451859821 ps
CPU time 2.95 seconds
Started Feb 25 12:37:10 PM PST 24
Finished Feb 25 12:37:14 PM PST 24
Peak memory 217024 kb
Host smart-9138fbf7-323c-45a8-8465-b428116dda73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642250759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr
_outstanding.642250759 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.520861121
Short name T91
Test name
Test status
Simulation time 145368173 ps
CPU time 1.31 seconds
Started Feb 25 12:37:15 PM PST 24
Finished Feb 25 12:37:17 PM PST 24
Peak memory 218360 kb
Host smart-d8387f9d-69f5-41d6-b46d-eae1909e7f09
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520861121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_
errors.520861121 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.3965114715
Short name T96
Test name
Test status
Simulation time 173868979 ps
CPU time 2.7 seconds
Started Feb 25 12:37:26 PM PST 24
Finished Feb 25 12:37:30 PM PST 24
Peak memory 217340 kb
Host smart-2446f819-435d-44ad-adeb-5e211fdc8a9a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965114715 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kma
c_shadow_reg_errors_with_csr_rw.3965114715 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/16.kmac_tl_errors.224216979
Short name T1096
Test name
Test status
Simulation time 272013650 ps
CPU time 2.49 seconds
Started Feb 25 12:37:10 PM PST 24
Finished Feb 25 12:37:13 PM PST 24
Peak memory 217116 kb
Host smart-092689aa-9e74-4006-a2f6-4f5d5f0701e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224216979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.224216979 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/16.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.3397541236
Short name T180
Test name
Test status
Simulation time 399037206 ps
CPU time 3.23 seconds
Started Feb 25 12:37:02 PM PST 24
Finished Feb 25 12:37:05 PM PST 24
Peak memory 217044 kb
Host smart-67186ff7-adf9-4ff8-bea7-c7d45c70f07e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397541236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.3397
541236 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1487846889
Short name T1166
Test name
Test status
Simulation time 22515862 ps
CPU time 1.43 seconds
Started Feb 25 12:37:14 PM PST 24
Finished Feb 25 12:37:16 PM PST 24
Peak memory 217996 kb
Host smart-88f2981d-708a-4f91-946b-228da7ce05bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487846889 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.1487846889 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/17.kmac_csr_rw.4240461475
Short name T1132
Test name
Test status
Simulation time 17742535 ps
CPU time 0.93 seconds
Started Feb 25 12:37:18 PM PST 24
Finished Feb 25 12:37:19 PM PST 24
Peak memory 216096 kb
Host smart-1b515504-1f2d-41da-9a7c-eb9af0a80816
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240461475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.4240461475 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/17.kmac_intr_test.1279289699
Short name T1160
Test name
Test status
Simulation time 13278190 ps
CPU time 0.82 seconds
Started Feb 25 12:37:12 PM PST 24
Finished Feb 25 12:37:13 PM PST 24
Peak memory 215936 kb
Host smart-2e24d9c2-5466-44b6-830f-0624d802c7b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279289699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.1279289699 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.677120575
Short name T1137
Test name
Test status
Simulation time 169170614 ps
CPU time 2.81 seconds
Started Feb 25 12:37:13 PM PST 24
Finished Feb 25 12:37:15 PM PST 24
Peak memory 216956 kb
Host smart-1505dad4-f5a1-4b7a-b5e2-a2a1432a2db3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677120575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_csr
_outstanding.677120575 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2841698545
Short name T1083
Test name
Test status
Simulation time 119046876 ps
CPU time 1.59 seconds
Started Feb 25 12:37:23 PM PST 24
Finished Feb 25 12:37:25 PM PST 24
Peak memory 224336 kb
Host smart-c7a2a8fc-b7e6-49b4-a4be-c8241378ad8e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841698545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg
_errors.2841698545 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.3934384141
Short name T1197
Test name
Test status
Simulation time 92021451 ps
CPU time 1.75 seconds
Started Feb 25 12:37:17 PM PST 24
Finished Feb 25 12:37:19 PM PST 24
Peak memory 224324 kb
Host smart-39600af4-7252-4588-9dc4-8b279ff83dd4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934384141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kma
c_shadow_reg_errors_with_csr_rw.3934384141 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/17.kmac_tl_errors.4137311072
Short name T1228
Test name
Test status
Simulation time 241628450 ps
CPU time 3.3 seconds
Started Feb 25 12:37:03 PM PST 24
Finished Feb 25 12:37:06 PM PST 24
Peak memory 217156 kb
Host smart-a8f5202e-63fe-478c-8e60-6c112da35984
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137311072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.4137311072 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.1577574834
Short name T182
Test name
Test status
Simulation time 581674077 ps
CPU time 3.06 seconds
Started Feb 25 12:37:21 PM PST 24
Finished Feb 25 12:37:24 PM PST 24
Peak memory 216252 kb
Host smart-4fd31398-366a-475d-a652-fc9b7820fdd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577574834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.1577
574834 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.1463077615
Short name T1227
Test name
Test status
Simulation time 419986810 ps
CPU time 1.81 seconds
Started Feb 25 12:37:27 PM PST 24
Finished Feb 25 12:37:29 PM PST 24
Peak memory 221116 kb
Host smart-0189c497-e969-4245-a34f-71378d0853b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463077615 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.1463077615 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/18.kmac_csr_rw.1614073761
Short name T1218
Test name
Test status
Simulation time 15741317 ps
CPU time 1.16 seconds
Started Feb 25 12:37:13 PM PST 24
Finished Feb 25 12:37:14 PM PST 24
Peak memory 216036 kb
Host smart-d308f928-0b37-4df6-87d5-e7e3a7659312
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614073761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.1614073761 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/18.kmac_intr_test.832095574
Short name T1082
Test name
Test status
Simulation time 26888474 ps
CPU time 0.82 seconds
Started Feb 25 12:37:12 PM PST 24
Finished Feb 25 12:37:13 PM PST 24
Peak memory 215976 kb
Host smart-d97305f9-e696-4d3d-9562-aa8cf3f07487
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832095574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.832095574 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/18.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.1452577910
Short name T1182
Test name
Test status
Simulation time 640079513 ps
CPU time 1.74 seconds
Started Feb 25 12:37:13 PM PST 24
Finished Feb 25 12:37:15 PM PST 24
Peak memory 216236 kb
Host smart-a7cc739b-99f7-449a-bc51-713e32d0f4dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452577910 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_cs
r_outstanding.1452577910 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1436894539
Short name T88
Test name
Test status
Simulation time 108618165 ps
CPU time 1.17 seconds
Started Feb 25 12:37:18 PM PST 24
Finished Feb 25 12:37:19 PM PST 24
Peak memory 224456 kb
Host smart-1e5c3dc0-38b7-4a71-b018-e9c0e69f0f14
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436894539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg
_errors.1436894539 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.1405308339
Short name T1235
Test name
Test status
Simulation time 282264479 ps
CPU time 2.23 seconds
Started Feb 25 12:37:05 PM PST 24
Finished Feb 25 12:37:08 PM PST 24
Peak memory 221240 kb
Host smart-daf0161a-787f-4768-a17a-e559a2c5df68
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405308339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kma
c_shadow_reg_errors_with_csr_rw.1405308339 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/18.kmac_tl_errors.1657812183
Short name T1136
Test name
Test status
Simulation time 154211093 ps
CPU time 2.56 seconds
Started Feb 25 12:37:29 PM PST 24
Finished Feb 25 12:37:32 PM PST 24
Peak memory 217176 kb
Host smart-460a4e25-c5a5-41d7-8ecc-af8093fda9d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657812183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.1657812183 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.1693277091
Short name T1185
Test name
Test status
Simulation time 45132650 ps
CPU time 2.52 seconds
Started Feb 25 12:37:17 PM PST 24
Finished Feb 25 12:37:20 PM PST 24
Peak memory 222092 kb
Host smart-05bee7c2-db41-4a5b-aac3-4a374eb6edb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693277091 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.1693277091 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/19.kmac_csr_rw.342079412
Short name T153
Test name
Test status
Simulation time 29530259 ps
CPU time 1.17 seconds
Started Feb 25 12:37:12 PM PST 24
Finished Feb 25 12:37:19 PM PST 24
Peak memory 217012 kb
Host smart-34867f59-fc08-4b63-987f-b9b801b6e0ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342079412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.342079412 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/19.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/19.kmac_intr_test.2060990865
Short name T1127
Test name
Test status
Simulation time 46037455 ps
CPU time 0.78 seconds
Started Feb 25 12:37:23 PM PST 24
Finished Feb 25 12:37:24 PM PST 24
Peak memory 216780 kb
Host smart-67aef188-9139-409c-92ea-9ff4ec9b1e74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060990865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.2060990865 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.937736892
Short name T1110
Test name
Test status
Simulation time 2318704641 ps
CPU time 3.26 seconds
Started Feb 25 12:37:04 PM PST 24
Finished Feb 25 12:37:08 PM PST 24
Peak memory 217116 kb
Host smart-83bb510e-afc9-4963-8b14-c3c7d7674c3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937736892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr
_outstanding.937736892 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.2270170759
Short name T94
Test name
Test status
Simulation time 260604697 ps
CPU time 1.17 seconds
Started Feb 25 12:37:12 PM PST 24
Finished Feb 25 12:37:14 PM PST 24
Peak memory 224300 kb
Host smart-84b5ea48-1a41-432b-ae96-8737a147f153
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270170759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg
_errors.2270170759 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.1723829215
Short name T97
Test name
Test status
Simulation time 360708270 ps
CPU time 3.02 seconds
Started Feb 25 12:37:31 PM PST 24
Finished Feb 25 12:37:34 PM PST 24
Peak memory 220112 kb
Host smart-fbd4b226-4249-4e75-909b-0ddcc4d51b87
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723829215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kma
c_shadow_reg_errors_with_csr_rw.1723829215 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/19.kmac_tl_errors.2116866430
Short name T1157
Test name
Test status
Simulation time 32845367 ps
CPU time 1.81 seconds
Started Feb 25 12:37:15 PM PST 24
Finished Feb 25 12:37:17 PM PST 24
Peak memory 216224 kb
Host smart-992a21b8-d2b8-4f8d-b6ac-e7a7d5a56fc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116866430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.2116866430 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.1117235741
Short name T117
Test name
Test status
Simulation time 810188386 ps
CPU time 5.29 seconds
Started Feb 25 12:37:32 PM PST 24
Finished Feb 25 12:37:37 PM PST 24
Peak memory 217088 kb
Host smart-13062099-9d8c-4787-bad9-2ea9c328cf23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117235741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.1117
235741 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.3217127236
Short name T1084
Test name
Test status
Simulation time 167158813 ps
CPU time 5.14 seconds
Started Feb 25 12:37:17 PM PST 24
Finished Feb 25 12:37:22 PM PST 24
Peak memory 217032 kb
Host smart-28e28a56-7f31-47fb-84e2-c164de5e9c4b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217127236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.3217127
236 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.177760561
Short name T1181
Test name
Test status
Simulation time 335832938 ps
CPU time 16.42 seconds
Started Feb 25 12:37:13 PM PST 24
Finished Feb 25 12:37:30 PM PST 24
Peak memory 215984 kb
Host smart-b8ed3227-2185-42ed-8256-9feb20622fb2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177760561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.17776056
1 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.1421480857
Short name T1221
Test name
Test status
Simulation time 51901453 ps
CPU time 1.15 seconds
Started Feb 25 12:36:59 PM PST 24
Finished Feb 25 12:37:00 PM PST 24
Peak memory 216892 kb
Host smart-1a546b80-b1b7-45e4-b1db-51c764bc9ca9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421480857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.1421480
857 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.2535618706
Short name T1196
Test name
Test status
Simulation time 207874217 ps
CPU time 3.19 seconds
Started Feb 25 12:37:11 PM PST 24
Finished Feb 25 12:37:15 PM PST 24
Peak memory 222224 kb
Host smart-81ad1f98-31c3-430e-b785-fedf916f9cd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535618706 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.2535618706 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/2.kmac_csr_rw.1586845293
Short name T1087
Test name
Test status
Simulation time 464389703 ps
CPU time 1.37 seconds
Started Feb 25 12:37:05 PM PST 24
Finished Feb 25 12:37:07 PM PST 24
Peak memory 217040 kb
Host smart-683b3726-9535-47a2-af72-3a2cb0a1d718
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586845293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.1586845293 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/2.kmac_intr_test.2530083480
Short name T1208
Test name
Test status
Simulation time 17189577 ps
CPU time 0.79 seconds
Started Feb 25 12:36:57 PM PST 24
Finished Feb 25 12:36:58 PM PST 24
Peak memory 216072 kb
Host smart-8f86c062-9df8-4edf-be71-19a1edf005a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530083480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.2530083480 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.1131077455
Short name T141
Test name
Test status
Simulation time 49943544 ps
CPU time 1.22 seconds
Started Feb 25 12:37:02 PM PST 24
Finished Feb 25 12:37:04 PM PST 24
Peak memory 216944 kb
Host smart-e2066470-3319-4891-9504-8a94afdc3bb1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131077455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partia
l_access.1131077455 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/2.kmac_mem_walk.1808951647
Short name T1090
Test name
Test status
Simulation time 14424935 ps
CPU time 0.77 seconds
Started Feb 25 12:37:14 PM PST 24
Finished Feb 25 12:37:15 PM PST 24
Peak memory 216196 kb
Host smart-7526498c-2afb-4536-8f5d-f15f8652203a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808951647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.1808951647
+enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.1470655100
Short name T1162
Test name
Test status
Simulation time 33631019 ps
CPU time 1.68 seconds
Started Feb 25 12:37:03 PM PST 24
Finished Feb 25 12:37:05 PM PST 24
Peak memory 216968 kb
Host smart-13976324-5391-456e-921a-b21a542dc07e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470655100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr
_outstanding.1470655100 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.1169812516
Short name T1184
Test name
Test status
Simulation time 166807124 ps
CPU time 1.33 seconds
Started Feb 25 12:36:53 PM PST 24
Finished Feb 25 12:36:55 PM PST 24
Peak memory 217288 kb
Host smart-1d06321f-e212-4b93-b531-3a98363b341f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169812516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_
errors.1169812516 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.179821194
Short name T115
Test name
Test status
Simulation time 337989059 ps
CPU time 2.03 seconds
Started Feb 25 12:37:00 PM PST 24
Finished Feb 25 12:37:02 PM PST 24
Peak memory 219716 kb
Host smart-306b4f55-6be9-4197-8216-46a879b09a9b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179821194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_
shadow_reg_errors_with_csr_rw.179821194 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/2.kmac_tl_errors.2387860171
Short name T1103
Test name
Test status
Simulation time 59769898 ps
CPU time 1.96 seconds
Started Feb 25 12:37:02 PM PST 24
Finished Feb 25 12:37:04 PM PST 24
Peak memory 216376 kb
Host smart-678a7198-a957-4b62-a5dc-a4aa552f122a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387860171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.2387860171 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/20.kmac_intr_test.1701539543
Short name T184
Test name
Test status
Simulation time 14950599 ps
CPU time 0.78 seconds
Started Feb 25 12:37:24 PM PST 24
Finished Feb 25 12:37:25 PM PST 24
Peak memory 216824 kb
Host smart-f2a33dfc-60c2-4ed9-a333-d64c4f81035b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701539543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.1701539543 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/21.kmac_intr_test.3289419317
Short name T1133
Test name
Test status
Simulation time 15590625 ps
CPU time 0.86 seconds
Started Feb 25 12:37:29 PM PST 24
Finished Feb 25 12:37:30 PM PST 24
Peak memory 216952 kb
Host smart-a0d9f9aa-9469-478f-ae7c-730609b878ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289419317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.3289419317 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/22.kmac_intr_test.3696195574
Short name T1138
Test name
Test status
Simulation time 43553810 ps
CPU time 0.76 seconds
Started Feb 25 12:37:28 PM PST 24
Finished Feb 25 12:37:29 PM PST 24
Peak memory 216848 kb
Host smart-9a4dec8c-acc2-46a3-acec-61f42cc5d9e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696195574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.3696195574 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/23.kmac_intr_test.1035265738
Short name T1106
Test name
Test status
Simulation time 74779516 ps
CPU time 0.85 seconds
Started Feb 25 12:37:31 PM PST 24
Finished Feb 25 12:37:32 PM PST 24
Peak memory 216020 kb
Host smart-fa343cd0-c5df-4262-8d5c-2a64175dd2f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035265738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.1035265738 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/24.kmac_intr_test.1737516482
Short name T1121
Test name
Test status
Simulation time 17117374 ps
CPU time 0.8 seconds
Started Feb 25 12:37:27 PM PST 24
Finished Feb 25 12:37:28 PM PST 24
Peak memory 215772 kb
Host smart-7a7c80ce-c5e0-4f98-93ec-1bbb2d094be8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737516482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.1737516482 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/26.kmac_intr_test.3904309339
Short name T1242
Test name
Test status
Simulation time 53090715 ps
CPU time 0.81 seconds
Started Feb 25 12:37:22 PM PST 24
Finished Feb 25 12:37:23 PM PST 24
Peak memory 216872 kb
Host smart-4218862b-594e-44a7-981d-d185c3230098
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904309339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.3904309339 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/27.kmac_intr_test.2385346197
Short name T1113
Test name
Test status
Simulation time 13822811 ps
CPU time 0.82 seconds
Started Feb 25 12:37:23 PM PST 24
Finished Feb 25 12:37:24 PM PST 24
Peak memory 216792 kb
Host smart-368ca9e3-8976-4782-b728-e7ad5482e8c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385346197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.2385346197 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/28.kmac_intr_test.125390611
Short name T1233
Test name
Test status
Simulation time 24136510 ps
CPU time 0.79 seconds
Started Feb 25 12:37:19 PM PST 24
Finished Feb 25 12:37:21 PM PST 24
Peak memory 216788 kb
Host smart-0530356c-4642-44be-830c-74e9ca5ec49b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125390611 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.125390611 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/28.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/29.kmac_intr_test.1714872827
Short name T1143
Test name
Test status
Simulation time 14981640 ps
CPU time 0.82 seconds
Started Feb 25 12:37:33 PM PST 24
Finished Feb 25 12:37:34 PM PST 24
Peak memory 216876 kb
Host smart-3d99acce-b9db-44b8-8838-89ecf6d186ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714872827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.1714872827 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.665554902
Short name T1190
Test name
Test status
Simulation time 149811764 ps
CPU time 9.6 seconds
Started Feb 25 12:37:02 PM PST 24
Finished Feb 25 12:37:12 PM PST 24
Peak memory 217116 kb
Host smart-df283dc2-66fb-480b-ae1a-b95928d72eee
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665554902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.66555490
2 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.322231846
Short name T1231
Test name
Test status
Simulation time 640570752 ps
CPU time 9.03 seconds
Started Feb 25 12:37:19 PM PST 24
Finished Feb 25 12:37:28 PM PST 24
Peak memory 216028 kb
Host smart-6cc519c0-333f-4c42-8cea-e5aae35d5746
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322231846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.32223184
6 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.1514853919
Short name T155
Test name
Test status
Simulation time 39508642 ps
CPU time 0.99 seconds
Started Feb 25 12:37:08 PM PST 24
Finished Feb 25 12:37:09 PM PST 24
Peak memory 216884 kb
Host smart-ad132fa4-72de-42ac-9b8e-95d20620a996
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514853919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.1514853
919 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.3855158111
Short name T1125
Test name
Test status
Simulation time 265879109 ps
CPU time 2.36 seconds
Started Feb 25 12:37:01 PM PST 24
Finished Feb 25 12:37:03 PM PST 24
Peak memory 222128 kb
Host smart-5ab134d3-b019-40a8-880d-640032fada19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855158111 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.3855158111 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/3.kmac_csr_rw.4171733370
Short name T1129
Test name
Test status
Simulation time 21547450 ps
CPU time 1.04 seconds
Started Feb 25 12:37:05 PM PST 24
Finished Feb 25 12:37:06 PM PST 24
Peak memory 216816 kb
Host smart-ed2d113c-8fd4-4dd7-8213-ae99390baf67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171733370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.4171733370 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/3.kmac_intr_test.16366522
Short name T1178
Test name
Test status
Simulation time 58501358 ps
CPU time 0.82 seconds
Started Feb 25 12:36:54 PM PST 24
Finished Feb 25 12:36:55 PM PST 24
Peak memory 216872 kb
Host smart-0dbff308-1179-4560-b4b2-6b6a857b8246
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16366522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.16366522 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/3.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.1387781275
Short name T143
Test name
Test status
Simulation time 46994673 ps
CPU time 1.11 seconds
Started Feb 25 12:37:04 PM PST 24
Finished Feb 25 12:37:05 PM PST 24
Peak memory 216184 kb
Host smart-5baa68eb-d57b-4e38-af32-612ef215ed57
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387781275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partia
l_access.1387781275 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/3.kmac_mem_walk.2468012048
Short name T1213
Test name
Test status
Simulation time 36169476 ps
CPU time 0.78 seconds
Started Feb 25 12:36:57 PM PST 24
Finished Feb 25 12:36:58 PM PST 24
Peak memory 216824 kb
Host smart-60810cbf-b299-4492-b020-36f2b852b06a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468012048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.2468012048
+enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.3057097678
Short name T1192
Test name
Test status
Simulation time 49585894 ps
CPU time 1.68 seconds
Started Feb 25 12:37:02 PM PST 24
Finished Feb 25 12:37:04 PM PST 24
Peak memory 216964 kb
Host smart-aab3c630-57cd-43f8-adc8-6a893a96cd24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057097678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr
_outstanding.3057097678 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.250158987
Short name T1236
Test name
Test status
Simulation time 68237660 ps
CPU time 1.59 seconds
Started Feb 25 12:37:19 PM PST 24
Finished Feb 25 12:37:20 PM PST 24
Peak memory 217956 kb
Host smart-1d1d3dd1-6187-4099-8ad9-91435770db53
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250158987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_e
rrors.250158987 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.620638856
Short name T1237
Test name
Test status
Simulation time 116742863 ps
CPU time 1.73 seconds
Started Feb 25 12:36:57 PM PST 24
Finished Feb 25 12:36:59 PM PST 24
Peak memory 216292 kb
Host smart-24a81c7a-e4f7-47e9-86c4-11dcb9b59e5f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620638856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_
shadow_reg_errors_with_csr_rw.620638856 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/3.kmac_tl_errors.3704920191
Short name T1210
Test name
Test status
Simulation time 153984038 ps
CPU time 2.9 seconds
Started Feb 25 12:37:01 PM PST 24
Finished Feb 25 12:37:04 PM PST 24
Peak memory 217316 kb
Host smart-fc816860-4057-4b08-b6ec-259063138204
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704920191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.3704920191 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.1920026470
Short name T1164
Test name
Test status
Simulation time 214226621 ps
CPU time 4.64 seconds
Started Feb 25 12:36:59 PM PST 24
Finished Feb 25 12:37:04 PM PST 24
Peak memory 216952 kb
Host smart-73caf7ee-5912-46d9-8234-050eda8c54dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920026470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.19200
26470 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/30.kmac_intr_test.2744768568
Short name T1167
Test name
Test status
Simulation time 15632811 ps
CPU time 0.83 seconds
Started Feb 25 12:37:39 PM PST 24
Finished Feb 25 12:37:40 PM PST 24
Peak memory 216880 kb
Host smart-40c9e06c-b60d-48fe-a130-296f2bee3e31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744768568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.2744768568 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/31.kmac_intr_test.1789335252
Short name T1108
Test name
Test status
Simulation time 37578612 ps
CPU time 0.82 seconds
Started Feb 25 12:37:06 PM PST 24
Finished Feb 25 12:37:07 PM PST 24
Peak memory 216876 kb
Host smart-a78c6fc4-6f01-45b3-9318-4f64559daed8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789335252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.1789335252 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/33.kmac_intr_test.1142477202
Short name T1230
Test name
Test status
Simulation time 16103687 ps
CPU time 0.81 seconds
Started Feb 25 12:37:16 PM PST 24
Finished Feb 25 12:37:17 PM PST 24
Peak memory 215988 kb
Host smart-8d8f80d8-d314-4fdb-bcf2-8bfa9432cd5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142477202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.1142477202 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/34.kmac_intr_test.533715267
Short name T1146
Test name
Test status
Simulation time 19403529 ps
CPU time 0.84 seconds
Started Feb 25 12:37:35 PM PST 24
Finished Feb 25 12:37:36 PM PST 24
Peak memory 216876 kb
Host smart-4eb292d2-c239-46cf-ab41-d21b447d491c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533715267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.533715267 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/34.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/35.kmac_intr_test.1946301728
Short name T1200
Test name
Test status
Simulation time 17642193 ps
CPU time 0.76 seconds
Started Feb 25 12:37:21 PM PST 24
Finished Feb 25 12:37:21 PM PST 24
Peak memory 216832 kb
Host smart-87c036f7-26a4-417e-82ca-1b479100f0d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946301728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.1946301728 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/36.kmac_intr_test.2505096920
Short name T121
Test name
Test status
Simulation time 14950894 ps
CPU time 0.83 seconds
Started Feb 25 12:37:28 PM PST 24
Finished Feb 25 12:37:29 PM PST 24
Peak memory 216692 kb
Host smart-7175883a-dda2-4fd7-a443-94079f561da9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505096920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.2505096920 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/37.kmac_intr_test.3523672175
Short name T1119
Test name
Test status
Simulation time 78329549 ps
CPU time 0.76 seconds
Started Feb 25 12:37:23 PM PST 24
Finished Feb 25 12:37:24 PM PST 24
Peak memory 216832 kb
Host smart-e5c79e34-0b62-453a-a327-1b5ce2f0ecff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523672175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.3523672175 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/38.kmac_intr_test.1293355500
Short name T1191
Test name
Test status
Simulation time 27724887 ps
CPU time 0.83 seconds
Started Feb 25 12:37:24 PM PST 24
Finished Feb 25 12:37:25 PM PST 24
Peak memory 215920 kb
Host smart-28bd0cd7-8e4b-4dc9-8ca8-baa08e33e9c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293355500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.1293355500 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/39.kmac_intr_test.1625521223
Short name T1212
Test name
Test status
Simulation time 35262966 ps
CPU time 0.86 seconds
Started Feb 25 12:37:03 PM PST 24
Finished Feb 25 12:37:04 PM PST 24
Peak memory 216088 kb
Host smart-9dc55ee1-dce3-4135-9522-7396e0733723
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625521223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.1625521223 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.3700956017
Short name T1238
Test name
Test status
Simulation time 531842027 ps
CPU time 11.49 seconds
Started Feb 25 12:37:01 PM PST 24
Finished Feb 25 12:37:12 PM PST 24
Peak memory 216344 kb
Host smart-434f8e28-9be0-4f76-9e00-b2ac544f9ce6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700956017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.3700956
017 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.1282732054
Short name T1095
Test name
Test status
Simulation time 9440700237 ps
CPU time 21.02 seconds
Started Feb 25 12:37:04 PM PST 24
Finished Feb 25 12:37:25 PM PST 24
Peak memory 216168 kb
Host smart-511ba477-622a-4cce-ba70-006326e69aed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282732054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.1282732
054 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.3386232647
Short name T1139
Test name
Test status
Simulation time 71166034 ps
CPU time 1.04 seconds
Started Feb 25 12:37:04 PM PST 24
Finished Feb 25 12:37:05 PM PST 24
Peak memory 216116 kb
Host smart-26b3108f-d1bf-453d-87ab-f2234b408305
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386232647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.3386232
647 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.4039787131
Short name T1097
Test name
Test status
Simulation time 100000675 ps
CPU time 2.85 seconds
Started Feb 25 12:37:03 PM PST 24
Finished Feb 25 12:37:06 PM PST 24
Peak memory 222596 kb
Host smart-2acbcdc2-7eb8-4eed-becc-c9bcb46a8f5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039787131 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.4039787131 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/4.kmac_csr_rw.4193350523
Short name T1161
Test name
Test status
Simulation time 25559445 ps
CPU time 1.03 seconds
Started Feb 25 12:36:58 PM PST 24
Finished Feb 25 12:37:00 PM PST 24
Peak memory 216876 kb
Host smart-236a8d73-a093-4a76-b524-ed64e02c5644
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193350523 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.4193350523 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/4.kmac_intr_test.410252823
Short name T1102
Test name
Test status
Simulation time 21437133 ps
CPU time 0.81 seconds
Started Feb 25 12:37:09 PM PST 24
Finished Feb 25 12:37:11 PM PST 24
Peak memory 216112 kb
Host smart-d481bd3e-ef53-482c-9d9c-5e6eb6b7b91a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410252823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.410252823 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/4.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.3945052295
Short name T144
Test name
Test status
Simulation time 44586084 ps
CPU time 1.46 seconds
Started Feb 25 12:37:10 PM PST 24
Finished Feb 25 12:37:11 PM PST 24
Peak memory 216996 kb
Host smart-95a54e9c-556f-40ee-9c6a-787e2ec39483
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945052295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partia
l_access.3945052295 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/4.kmac_mem_walk.3110291602
Short name T1089
Test name
Test status
Simulation time 20847993 ps
CPU time 0.75 seconds
Started Feb 25 12:37:02 PM PST 24
Finished Feb 25 12:37:08 PM PST 24
Peak memory 216116 kb
Host smart-c0b91a1e-4b3f-4890-b22d-d8ad31a6747e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110291602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.3110291602
+enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.4049247651
Short name T1098
Test name
Test status
Simulation time 42388862 ps
CPU time 1.48 seconds
Started Feb 25 12:36:58 PM PST 24
Finished Feb 25 12:37:00 PM PST 24
Peak memory 216196 kb
Host smart-7937c6c7-7e17-4527-9337-a792a0a96941
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049247651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr
_outstanding.4049247651 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.3737727779
Short name T1169
Test name
Test status
Simulation time 41500070 ps
CPU time 0.84 seconds
Started Feb 25 12:37:04 PM PST 24
Finished Feb 25 12:37:04 PM PST 24
Peak memory 219044 kb
Host smart-3bc79435-0002-4b37-a6cc-105ebeb8ac48
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737727779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_
errors.3737727779 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.2039524524
Short name T1172
Test name
Test status
Simulation time 53185286 ps
CPU time 2.79 seconds
Started Feb 25 12:37:15 PM PST 24
Finished Feb 25 12:37:17 PM PST 24
Peak memory 220072 kb
Host smart-87acde70-6343-4357-82ff-174aa3029bd8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039524524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac
_shadow_reg_errors_with_csr_rw.2039524524 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/4.kmac_tl_errors.831165144
Short name T1163
Test name
Test status
Simulation time 211471328 ps
CPU time 3.74 seconds
Started Feb 25 12:37:14 PM PST 24
Finished Feb 25 12:37:18 PM PST 24
Peak memory 216256 kb
Host smart-0cc2c740-5c4d-473c-85ba-9aa82f40b502
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831165144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.831165144 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/4.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/40.kmac_intr_test.3526111619
Short name T185
Test name
Test status
Simulation time 35148937 ps
CPU time 0.76 seconds
Started Feb 25 12:37:40 PM PST 24
Finished Feb 25 12:37:41 PM PST 24
Peak memory 216724 kb
Host smart-a59c805a-17d4-413d-b23f-f007a87a83d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526111619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.3526111619 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/41.kmac_intr_test.3059655259
Short name T1142
Test name
Test status
Simulation time 13708836 ps
CPU time 0.76 seconds
Started Feb 25 12:37:32 PM PST 24
Finished Feb 25 12:37:32 PM PST 24
Peak memory 216796 kb
Host smart-26c7e959-33b2-4b79-b1c2-af0b937a8d04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059655259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.3059655259 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/42.kmac_intr_test.1312791761
Short name T1141
Test name
Test status
Simulation time 43361140 ps
CPU time 0.82 seconds
Started Feb 25 12:37:22 PM PST 24
Finished Feb 25 12:37:23 PM PST 24
Peak memory 216900 kb
Host smart-65160c31-a55a-4c80-8625-09de5fc0f94e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312791761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.1312791761 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/43.kmac_intr_test.1193666647
Short name T1159
Test name
Test status
Simulation time 28432385 ps
CPU time 0.85 seconds
Started Feb 25 12:37:32 PM PST 24
Finished Feb 25 12:37:33 PM PST 24
Peak memory 216012 kb
Host smart-0d53efd1-4367-4ddd-8414-555b6c1c69c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193666647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.1193666647 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/44.kmac_intr_test.3457853328
Short name T1224
Test name
Test status
Simulation time 27559984 ps
CPU time 0.81 seconds
Started Feb 25 12:37:23 PM PST 24
Finished Feb 25 12:37:24 PM PST 24
Peak memory 216932 kb
Host smart-43ee8d55-c7fe-4a8a-b704-6dd0f711d3a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457853328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.3457853328 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/45.kmac_intr_test.1372079213
Short name T1223
Test name
Test status
Simulation time 33181041 ps
CPU time 0.8 seconds
Started Feb 25 12:37:42 PM PST 24
Finished Feb 25 12:37:43 PM PST 24
Peak memory 216092 kb
Host smart-33a2916d-cd8b-444c-a51c-eaa394100943
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372079213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.1372079213 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/46.kmac_intr_test.4126882849
Short name T1131
Test name
Test status
Simulation time 29229190 ps
CPU time 0.79 seconds
Started Feb 25 12:37:19 PM PST 24
Finished Feb 25 12:37:20 PM PST 24
Peak memory 216788 kb
Host smart-6b753c51-b41f-4cae-9c16-6c8387002927
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126882849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.4126882849 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/47.kmac_intr_test.2083949526
Short name T1130
Test name
Test status
Simulation time 40825178 ps
CPU time 0.78 seconds
Started Feb 25 12:37:34 PM PST 24
Finished Feb 25 12:37:35 PM PST 24
Peak memory 216796 kb
Host smart-dad29d08-9717-47ee-ad69-f9693eebe9c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083949526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.2083949526 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/48.kmac_intr_test.3260783524
Short name T1104
Test name
Test status
Simulation time 37030933 ps
CPU time 0.8 seconds
Started Feb 25 12:37:21 PM PST 24
Finished Feb 25 12:37:23 PM PST 24
Peak memory 216776 kb
Host smart-3b32d0c9-1fe5-48c0-8eff-0514ca486d1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260783524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.3260783524 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/49.kmac_intr_test.3125733702
Short name T1092
Test name
Test status
Simulation time 33245794 ps
CPU time 0.78 seconds
Started Feb 25 12:37:24 PM PST 24
Finished Feb 25 12:37:25 PM PST 24
Peak memory 215960 kb
Host smart-30fd7fa7-b8a3-409a-903f-4eea9373bff0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125733702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.3125733702 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.4065979888
Short name T1194
Test name
Test status
Simulation time 59705158 ps
CPU time 1.66 seconds
Started Feb 25 12:36:52 PM PST 24
Finished Feb 25 12:36:54 PM PST 24
Peak memory 220468 kb
Host smart-3dd3ed3c-b240-48c3-8a6b-5c55d3b90d54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065979888 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.4065979888 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/5.kmac_csr_rw.768946659
Short name T1086
Test name
Test status
Simulation time 42267235 ps
CPU time 0.96 seconds
Started Feb 25 12:37:12 PM PST 24
Finished Feb 25 12:37:13 PM PST 24
Peak memory 216020 kb
Host smart-38a56364-c160-42f2-9b72-106395b0d137
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768946659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.768946659 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/5.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/5.kmac_intr_test.677767367
Short name T1099
Test name
Test status
Simulation time 44542125 ps
CPU time 0.81 seconds
Started Feb 25 12:37:03 PM PST 24
Finished Feb 25 12:37:04 PM PST 24
Peak memory 216876 kb
Host smart-1e6f842b-8f7d-4eec-aec3-97deebb71ed0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677767367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.677767367 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/5.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.302529650
Short name T1158
Test name
Test status
Simulation time 1720370201 ps
CPU time 2.9 seconds
Started Feb 25 12:37:04 PM PST 24
Finished Feb 25 12:37:07 PM PST 24
Peak memory 217048 kb
Host smart-d432feb2-1355-449e-8f4d-a3f41d68f63c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302529650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr_
outstanding.302529650 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.2413692128
Short name T90
Test name
Test status
Simulation time 26562385 ps
CPU time 1.08 seconds
Started Feb 25 12:37:06 PM PST 24
Finished Feb 25 12:37:07 PM PST 24
Peak memory 216916 kb
Host smart-0092def6-d810-4a68-92bd-2186fec08a5a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413692128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_
errors.2413692128 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/5.kmac_tl_errors.2351844609
Short name T1215
Test name
Test status
Simulation time 127417442 ps
CPU time 3.31 seconds
Started Feb 25 12:37:15 PM PST 24
Finished Feb 25 12:37:19 PM PST 24
Peak memory 217320 kb
Host smart-6a9bade9-93fc-477d-b78a-4da4195d60f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351844609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.2351844609 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.994304979
Short name T1155
Test name
Test status
Simulation time 300686611 ps
CPU time 5.07 seconds
Started Feb 25 12:37:12 PM PST 24
Finished Feb 25 12:37:17 PM PST 24
Peak memory 216952 kb
Host smart-b9534c7a-8945-468a-bca4-09af5c6b316e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994304979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.994304
979 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.1105041135
Short name T1100
Test name
Test status
Simulation time 78273678 ps
CPU time 2.37 seconds
Started Feb 25 12:37:08 PM PST 24
Finished Feb 25 12:37:10 PM PST 24
Peak memory 223796 kb
Host smart-a8f77dee-4797-49b8-a5b5-66cfa653ffe1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105041135 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.1105041135 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/6.kmac_csr_rw.3964676760
Short name T1145
Test name
Test status
Simulation time 256875743 ps
CPU time 1.01 seconds
Started Feb 25 12:37:24 PM PST 24
Finished Feb 25 12:37:25 PM PST 24
Peak memory 216976 kb
Host smart-b1e4b5a7-9186-4103-8d3e-1680ef4ccb9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964676760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.3964676760 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/6.kmac_intr_test.2038542009
Short name T1234
Test name
Test status
Simulation time 14511995 ps
CPU time 0.85 seconds
Started Feb 25 12:37:05 PM PST 24
Finished Feb 25 12:37:06 PM PST 24
Peak memory 216900 kb
Host smart-641d14ef-439e-41cb-9c4f-a0faf0cecc5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038542009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.2038542009 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.1257435532
Short name T1085
Test name
Test status
Simulation time 201350596 ps
CPU time 1.52 seconds
Started Feb 25 12:37:00 PM PST 24
Finished Feb 25 12:37:01 PM PST 24
Peak memory 216964 kb
Host smart-63243da5-af16-48fe-bd22-8b8cca8042fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257435532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr
_outstanding.1257435532 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.2720658419
Short name T1149
Test name
Test status
Simulation time 80233863 ps
CPU time 1.24 seconds
Started Feb 25 12:36:59 PM PST 24
Finished Feb 25 12:37:01 PM PST 24
Peak memory 224240 kb
Host smart-14c9c41c-eb24-4764-af0a-9c6dd503e007
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720658419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_
errors.2720658419 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.80550220
Short name T1174
Test name
Test status
Simulation time 97295349 ps
CPU time 2.71 seconds
Started Feb 25 12:37:16 PM PST 24
Finished Feb 25 12:37:19 PM PST 24
Peak memory 220460 kb
Host smart-de8505bf-a745-4535-8458-4ed0601aabdd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80550220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_s
hadow_reg_errors_with_csr_rw.80550220 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/6.kmac_tl_errors.2071693161
Short name T1186
Test name
Test status
Simulation time 79253003 ps
CPU time 1.62 seconds
Started Feb 25 12:36:54 PM PST 24
Finished Feb 25 12:36:56 PM PST 24
Peak memory 217216 kb
Host smart-2c69a1eb-2d38-49d2-afa4-89c29c454b74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071693161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.2071693161 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.382622916
Short name T1134
Test name
Test status
Simulation time 108551620 ps
CPU time 3.32 seconds
Started Feb 25 12:37:00 PM PST 24
Finished Feb 25 12:37:04 PM PST 24
Peak memory 216952 kb
Host smart-74c97676-e534-4825-8ac3-fe1f5aeb19b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382622916 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.382622
916 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.2754838708
Short name T1126
Test name
Test status
Simulation time 381722042 ps
CPU time 3.12 seconds
Started Feb 25 12:37:02 PM PST 24
Finished Feb 25 12:37:06 PM PST 24
Peak memory 224144 kb
Host smart-316c6ff1-b94e-43ea-bc1d-11468603e470
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754838708 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.2754838708 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/7.kmac_csr_rw.1992906530
Short name T1079
Test name
Test status
Simulation time 22490394 ps
CPU time 0.96 seconds
Started Feb 25 12:37:07 PM PST 24
Finished Feb 25 12:37:09 PM PST 24
Peak memory 216860 kb
Host smart-374c7bd4-349a-4bb5-98db-93f71d5997e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992906530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.1992906530 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/7.kmac_intr_test.1586030681
Short name T1111
Test name
Test status
Simulation time 29229926 ps
CPU time 0.8 seconds
Started Feb 25 12:37:03 PM PST 24
Finished Feb 25 12:37:04 PM PST 24
Peak memory 216792 kb
Host smart-c759c1cf-ec4a-47f7-ad59-39208031106e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586030681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.1586030681 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.157116314
Short name T1202
Test name
Test status
Simulation time 35706323 ps
CPU time 1.65 seconds
Started Feb 25 12:37:04 PM PST 24
Finished Feb 25 12:37:05 PM PST 24
Peak memory 217032 kb
Host smart-6094a023-f552-41a7-baf4-69e3485bf854
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157116314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr_
outstanding.157116314 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2432829137
Short name T1135
Test name
Test status
Simulation time 158604819 ps
CPU time 1.09 seconds
Started Feb 25 12:37:01 PM PST 24
Finished Feb 25 12:37:02 PM PST 24
Peak memory 218392 kb
Host smart-e4544848-06d9-4520-ac04-a37c74954606
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432829137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_
errors.2432829137 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.192781685
Short name T1217
Test name
Test status
Simulation time 737441683 ps
CPU time 3.34 seconds
Started Feb 25 12:37:03 PM PST 24
Finished Feb 25 12:37:06 PM PST 24
Peak memory 221244 kb
Host smart-e370e966-4525-433e-b0d9-faa1fb61c706
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192781685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_
shadow_reg_errors_with_csr_rw.192781685 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/7.kmac_tl_errors.2507571988
Short name T1128
Test name
Test status
Simulation time 555223641 ps
CPU time 2.25 seconds
Started Feb 25 12:37:06 PM PST 24
Finished Feb 25 12:37:09 PM PST 24
Peak memory 217264 kb
Host smart-706e5fa6-2a82-49ae-b08c-37860f26f424
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507571988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.2507571988 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.3429393249
Short name T118
Test name
Test status
Simulation time 651749293 ps
CPU time 3.21 seconds
Started Feb 25 12:37:06 PM PST 24
Finished Feb 25 12:37:10 PM PST 24
Peak memory 216964 kb
Host smart-f76233c0-6bbf-4175-b3d4-244d0205a588
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429393249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.34293
93249 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.3698464435
Short name T1148
Test name
Test status
Simulation time 72717317 ps
CPU time 2.44 seconds
Started Feb 25 12:37:17 PM PST 24
Finished Feb 25 12:37:20 PM PST 24
Peak memory 222068 kb
Host smart-2e818125-ed6d-468f-b203-8cc77880841e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698464435 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.3698464435 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/8.kmac_csr_rw.2036224525
Short name T1198
Test name
Test status
Simulation time 14976299 ps
CPU time 1 seconds
Started Feb 25 12:37:02 PM PST 24
Finished Feb 25 12:37:04 PM PST 24
Peak memory 217052 kb
Host smart-5ae0521b-1022-4a8c-80fd-33382d34720a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036224525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.2036224525 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/8.kmac_intr_test.2722748317
Short name T120
Test name
Test status
Simulation time 21437001 ps
CPU time 0.84 seconds
Started Feb 25 12:37:04 PM PST 24
Finished Feb 25 12:37:04 PM PST 24
Peak memory 216808 kb
Host smart-ae9a3f8b-3fd4-495d-8693-db5c9b0b3a32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722748317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.2722748317 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.3382838267
Short name T1239
Test name
Test status
Simulation time 206865037 ps
CPU time 1.9 seconds
Started Feb 25 12:37:01 PM PST 24
Finished Feb 25 12:37:03 PM PST 24
Peak memory 217040 kb
Host smart-357db3b1-d3eb-43c8-8f4d-1cf7e6a9e2d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382838267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr
_outstanding.3382838267 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.2839731017
Short name T1180
Test name
Test status
Simulation time 257542172 ps
CPU time 1.14 seconds
Started Feb 25 12:37:12 PM PST 24
Finished Feb 25 12:37:14 PM PST 24
Peak memory 218316 kb
Host smart-958d0e12-5018-4bfe-82a1-148ecb4e085c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839731017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_
errors.2839731017 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.1441123309
Short name T1241
Test name
Test status
Simulation time 47737905 ps
CPU time 1.51 seconds
Started Feb 25 12:37:13 PM PST 24
Finished Feb 25 12:37:15 PM PST 24
Peak memory 217064 kb
Host smart-13cc4aac-3bf3-44ee-95a3-60d69a1aa7e5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441123309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac
_shadow_reg_errors_with_csr_rw.1441123309 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/8.kmac_tl_errors.2892826895
Short name T1101
Test name
Test status
Simulation time 42892611 ps
CPU time 1.54 seconds
Started Feb 25 12:37:16 PM PST 24
Finished Feb 25 12:37:18 PM PST 24
Peak memory 216276 kb
Host smart-0d566ba6-971e-4697-a880-ffa8c1e3ea1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892826895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.2892826895 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.4043040752
Short name T1170
Test name
Test status
Simulation time 1078887143 ps
CPU time 5.89 seconds
Started Feb 25 12:37:03 PM PST 24
Finished Feb 25 12:37:09 PM PST 24
Peak memory 217192 kb
Host smart-d488722c-1e4f-4e1a-9ff2-3b5571e91a7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043040752 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.40430
40752 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2603878859
Short name T1140
Test name
Test status
Simulation time 77800452 ps
CPU time 2.56 seconds
Started Feb 25 12:37:23 PM PST 24
Finished Feb 25 12:37:26 PM PST 24
Peak memory 222472 kb
Host smart-ba7a0453-5470-4b97-8fb7-82900551cb16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603878859 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.2603878859 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/9.kmac_csr_rw.121734875
Short name T1183
Test name
Test status
Simulation time 23358619 ps
CPU time 1.15 seconds
Started Feb 25 12:37:01 PM PST 24
Finished Feb 25 12:37:03 PM PST 24
Peak memory 216132 kb
Host smart-61ba208d-e163-4b1c-8ecd-66e0b6be83aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121734875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.121734875 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/9.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/9.kmac_intr_test.1521661946
Short name T1107
Test name
Test status
Simulation time 43338026 ps
CPU time 0.76 seconds
Started Feb 25 12:37:05 PM PST 24
Finished Feb 25 12:37:06 PM PST 24
Peak memory 216760 kb
Host smart-712bf5e3-b554-437e-acd8-c1e1db0f4de9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521661946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.1521661946 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2064462925
Short name T1175
Test name
Test status
Simulation time 37766526 ps
CPU time 2.22 seconds
Started Feb 25 12:37:23 PM PST 24
Finished Feb 25 12:37:25 PM PST 24
Peak memory 217052 kb
Host smart-d5b0e20e-c424-4df7-b01e-92412639464c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064462925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr
_outstanding.2064462925 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.241995919
Short name T1094
Test name
Test status
Simulation time 95620309 ps
CPU time 1.24 seconds
Started Feb 25 12:37:18 PM PST 24
Finished Feb 25 12:37:19 PM PST 24
Peak memory 217280 kb
Host smart-450f307b-866d-409c-8cdd-62746dc70c1f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241995919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_e
rrors.241995919 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.1567669463
Short name T122
Test name
Test status
Simulation time 374457249 ps
CPU time 2.8 seconds
Started Feb 25 12:37:13 PM PST 24
Finished Feb 25 12:37:16 PM PST 24
Peak memory 220032 kb
Host smart-210a2455-9131-4d4a-a06a-aa84b8215d03
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567669463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac
_shadow_reg_errors_with_csr_rw.1567669463 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/9.kmac_tl_errors.1488860326
Short name T1076
Test name
Test status
Simulation time 20666578 ps
CPU time 1.34 seconds
Started Feb 25 12:37:19 PM PST 24
Finished Feb 25 12:37:20 PM PST 24
Peak memory 216884 kb
Host smart-7c1cd7a9-d884-4008-968d-f3cf28091bef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488860326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.1488860326 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.2702819487
Short name T178
Test name
Test status
Simulation time 141180447 ps
CPU time 3.29 seconds
Started Feb 25 12:37:03 PM PST 24
Finished Feb 25 12:37:06 PM PST 24
Peak memory 224016 kb
Host smart-e17116d8-c5ad-465e-b14b-96c5bcc7eab6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702819487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.27028
19487 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_tl_intg_err/latest


Test location /workspace/coverage/default/0.kmac_alert_test.490398620
Short name T571
Test name
Test status
Simulation time 20667745 ps
CPU time 0.9 seconds
Started Feb 25 01:55:16 PM PST 24
Finished Feb 25 01:55:17 PM PST 24
Peak memory 219324 kb
Host smart-ba227091-8715-4971-8f5e-6c8f05fdb1c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490398620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.490398620 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/0.kmac_alert_test/latest


Test location /workspace/coverage/default/0.kmac_app.3223717487
Short name T597
Test name
Test status
Simulation time 14538136808 ps
CPU time 353.99 seconds
Started Feb 25 01:55:10 PM PST 24
Finished Feb 25 02:01:05 PM PST 24
Peak memory 249608 kb
Host smart-3c57e5e7-3776-4ac3-884b-4d142c637754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223717487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.3223717487 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_app/latest


Test location /workspace/coverage/default/0.kmac_app_with_partial_data.76931436
Short name T504
Test name
Test status
Simulation time 23580164755 ps
CPU time 118.85 seconds
Started Feb 25 01:55:18 PM PST 24
Finished Feb 25 01:57:17 PM PST 24
Peak memory 236388 kb
Host smart-5a764686-1bb7-49bf-a75f-81ea6014e0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76931436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.76931436 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/0.kmac_app_with_partial_data/latest


Test location /workspace/coverage/default/0.kmac_burst_write.588714913
Short name T716
Test name
Test status
Simulation time 24703696725 ps
CPU time 1208.41 seconds
Started Feb 25 01:55:11 PM PST 24
Finished Feb 25 02:15:20 PM PST 24
Peak memory 238964 kb
Host smart-23386fc4-e351-4af2-a5b3-d0a90bb358c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588714913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.588714913 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_burst_write/latest


Test location /workspace/coverage/default/0.kmac_edn_timeout_error.3914990865
Short name T709
Test name
Test status
Simulation time 1701885659 ps
CPU time 10.21 seconds
Started Feb 25 01:55:11 PM PST 24
Finished Feb 25 01:55:22 PM PST 24
Peak memory 227020 kb
Host smart-6c2a41ec-c8f4-4dc9-acba-198b018c549b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3914990865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.3914990865 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/0.kmac_entropy_mode_error.4025052910
Short name T602
Test name
Test status
Simulation time 126541554 ps
CPU time 4.99 seconds
Started Feb 25 01:55:09 PM PST 24
Finished Feb 25 01:55:16 PM PST 24
Peak memory 222096 kb
Host smart-e4810518-374a-4d50-af14-d456e9f4273a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4025052910 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.4025052910 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/0.kmac_entropy_refresh.1632903659
Short name T833
Test name
Test status
Simulation time 17670170666 ps
CPU time 208.18 seconds
Started Feb 25 01:55:09 PM PST 24
Finished Feb 25 01:58:39 PM PST 24
Peak memory 243280 kb
Host smart-b86b94f3-27a4-40b1-80e4-28379e8cdc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632903659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.1632903659 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/0.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/0.kmac_key_error.295635383
Short name T997
Test name
Test status
Simulation time 71926118 ps
CPU time 1.21 seconds
Started Feb 25 01:55:15 PM PST 24
Finished Feb 25 01:55:16 PM PST 24
Peak memory 218184 kb
Host smart-be4a859a-ce0c-42d9-a104-be8fd0051ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295635383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.295635383 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_key_error/latest


Test location /workspace/coverage/default/0.kmac_long_msg_and_output.2399191278
Short name T630
Test name
Test status
Simulation time 1661921389 ps
CPU time 187.74 seconds
Started Feb 25 01:55:20 PM PST 24
Finished Feb 25 01:58:28 PM PST 24
Peak memory 242976 kb
Host smart-4cc6e67f-0dfb-4efb-9a2e-2ea059ed9b34
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399191278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_an
d_output.2399191278 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/0.kmac_mubi.1590628971
Short name T802
Test name
Test status
Simulation time 8740689743 ps
CPU time 324.85 seconds
Started Feb 25 01:55:20 PM PST 24
Finished Feb 25 02:00:45 PM PST 24
Peak memory 247784 kb
Host smart-ad0c0f28-1166-4271-b793-c546a3396e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590628971 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.1590628971 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mubi/latest


Test location /workspace/coverage/default/0.kmac_sideload.4169182722
Short name T294
Test name
Test status
Simulation time 163296240 ps
CPU time 2.89 seconds
Started Feb 25 01:55:11 PM PST 24
Finished Feb 25 01:55:14 PM PST 24
Peak memory 221892 kb
Host smart-48bda900-fc42-47a7-be46-39e867dc6136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169182722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.4169182722 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_sideload/latest


Test location /workspace/coverage/default/0.kmac_smoke.3435481336
Short name T506
Test name
Test status
Simulation time 6745695084 ps
CPU time 68.34 seconds
Started Feb 25 01:55:16 PM PST 24
Finished Feb 25 01:56:25 PM PST 24
Peak memory 220052 kb
Host smart-6dd5cdd9-06fe-4d64-ac76-0fb660013ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435481336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.3435481336 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_smoke/latest


Test location /workspace/coverage/default/0.kmac_stress_all.1357087745
Short name T641
Test name
Test status
Simulation time 248953306145 ps
CPU time 2504.83 seconds
Started Feb 25 01:55:16 PM PST 24
Finished Feb 25 02:37:01 PM PST 24
Peak memory 415024 kb
Host smart-69038d09-6bf5-4029-a898-ace017f9008e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1357087745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.1357087745 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all/latest


Test location /workspace/coverage/default/0.kmac_test_vectors_kmac.42487537
Short name T832
Test name
Test status
Simulation time 558594833 ps
CPU time 6.14 seconds
Started Feb 25 01:55:15 PM PST 24
Finished Feb 25 01:55:21 PM PST 24
Peak memory 218444 kb
Host smart-741e0cb7-3cd9-4878-a050-e3bd76d0d75e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42487537 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.kmac_test_vectors_kmac.42487537 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/0.kmac_test_vectors_kmac_xof.2649496948
Short name T882
Test name
Test status
Simulation time 998378451 ps
CPU time 6.39 seconds
Started Feb 25 01:55:10 PM PST 24
Finished Feb 25 01:55:17 PM PST 24
Peak memory 219908 kb
Host smart-8b0d71bf-35ed-43d4-b8a6-fe6ceb5609ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649496948 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.kmac_test_vectors_kmac_xof.2649496948 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_224.1236004900
Short name T721
Test name
Test status
Simulation time 275534527950 ps
CPU time 2260.86 seconds
Started Feb 25 01:55:15 PM PST 24
Finished Feb 25 02:32:56 PM PST 24
Peak memory 401452 kb
Host smart-0a0b2080-abe5-49a9-8bda-1e89f77542fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1236004900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.1236004900 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_256.3851250985
Short name T635
Test name
Test status
Simulation time 572045282612 ps
CPU time 2318.9 seconds
Started Feb 25 01:55:18 PM PST 24
Finished Feb 25 02:33:57 PM PST 24
Peak memory 394776 kb
Host smart-29b2ed5e-5bc9-4a56-918b-e3ea85818572
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3851250985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.3851250985 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_384.2008986
Short name T446
Test name
Test status
Simulation time 180483599687 ps
CPU time 1742.24 seconds
Started Feb 25 01:55:19 PM PST 24
Finished Feb 25 02:24:21 PM PST 24
Peak memory 334372 kb
Host smart-fc1187cd-c41a-48bc-8602-85ca0097c64a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2008986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.2008986 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_512.3009335645
Short name T992
Test name
Test status
Simulation time 202101836401 ps
CPU time 1431.62 seconds
Started Feb 25 01:55:13 PM PST 24
Finished Feb 25 02:19:04 PM PST 24
Peak memory 298228 kb
Host smart-52451416-6a40-4114-b6b7-901ca650f752
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3009335645 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.3009335645 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/0.kmac_test_vectors_shake_256.1468756469
Short name T606
Test name
Test status
Simulation time 595682714061 ps
CPU time 4839.66 seconds
Started Feb 25 01:55:19 PM PST 24
Finished Feb 25 03:15:59 PM PST 24
Peak memory 566252 kb
Host smart-1953c15d-9f56-4fcb-9c5d-8aa801b514fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1468756469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.1468756469 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/1.kmac_alert_test.3818950845
Short name T760
Test name
Test status
Simulation time 22896129 ps
CPU time 0.85 seconds
Started Feb 25 01:55:19 PM PST 24
Finished Feb 25 01:55:20 PM PST 24
Peak memory 219296 kb
Host smart-2a967f7c-fc8e-4d1b-9e7f-667bf917c2db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818950845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.3818950845 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_alert_test/latest


Test location /workspace/coverage/default/1.kmac_app.4022950548
Short name T792
Test name
Test status
Simulation time 18116221682 ps
CPU time 110.27 seconds
Started Feb 25 01:55:30 PM PST 24
Finished Feb 25 01:57:20 PM PST 24
Peak memory 233896 kb
Host smart-867af189-4e03-4451-af88-50098f3f7f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022950548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.4022950548 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_app/latest


Test location /workspace/coverage/default/1.kmac_app_with_partial_data.2433639484
Short name T224
Test name
Test status
Simulation time 1351351064 ps
CPU time 37.56 seconds
Started Feb 25 01:55:18 PM PST 24
Finished Feb 25 01:55:56 PM PST 24
Peak memory 235308 kb
Host smart-9bb00bd6-118e-4337-a45d-4cd02c16236f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433639484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.2433639484 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_app_with_partial_data/latest


Test location /workspace/coverage/default/1.kmac_burst_write.3388043531
Short name T464
Test name
Test status
Simulation time 23558014358 ps
CPU time 822.41 seconds
Started Feb 25 01:55:18 PM PST 24
Finished Feb 25 02:09:00 PM PST 24
Peak memory 242996 kb
Host smart-5c86a69a-5004-4df4-9328-bd2879c18fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388043531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.3388043531 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_burst_write/latest


Test location /workspace/coverage/default/1.kmac_edn_timeout_error.3220906846
Short name T756
Test name
Test status
Simulation time 61341488 ps
CPU time 1.25 seconds
Started Feb 25 01:55:17 PM PST 24
Finished Feb 25 01:55:18 PM PST 24
Peak memory 218236 kb
Host smart-d4218c43-67f6-4802-a6ed-392305aefd1a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3220906846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.3220906846 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/1.kmac_entropy_mode_error.1168761788
Short name T577
Test name
Test status
Simulation time 25252167 ps
CPU time 0.97 seconds
Started Feb 25 01:55:18 PM PST 24
Finished Feb 25 01:55:19 PM PST 24
Peak memory 218156 kb
Host smart-a280d863-92b0-48d9-89d0-43036fef7b43
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1168761788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.1168761788 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/1.kmac_entropy_ready_error.1061034395
Short name T696
Test name
Test status
Simulation time 9439712053 ps
CPU time 27.8 seconds
Started Feb 25 01:55:21 PM PST 24
Finished Feb 25 01:55:50 PM PST 24
Peak memory 219236 kb
Host smart-b1e1fe6c-29e1-45ff-b88f-c3b876e96a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061034395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.1061034395 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_ready_error/latest


Test location /workspace/coverage/default/1.kmac_entropy_refresh.2654986087
Short name T1073
Test name
Test status
Simulation time 31455700558 ps
CPU time 372.88 seconds
Started Feb 25 01:55:30 PM PST 24
Finished Feb 25 02:01:43 PM PST 24
Peak memory 251688 kb
Host smart-c60d90e8-ae2f-49ad-863d-e3f09e704c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654986087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.2654986087 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/1.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/1.kmac_error.124067202
Short name T587
Test name
Test status
Simulation time 15859643799 ps
CPU time 390.23 seconds
Started Feb 25 01:55:20 PM PST 24
Finished Feb 25 02:01:50 PM PST 24
Peak memory 267456 kb
Host smart-9a4973c1-68a4-402f-a41a-326b57957746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124067202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.124067202 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_error/latest


Test location /workspace/coverage/default/1.kmac_key_error.3230125849
Short name T137
Test name
Test status
Simulation time 2317823467 ps
CPU time 2.62 seconds
Started Feb 25 01:55:21 PM PST 24
Finished Feb 25 01:55:23 PM PST 24
Peak memory 218280 kb
Host smart-ce2503b1-c7f0-4031-806d-e194817f936a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230125849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.3230125849 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_key_error/latest


Test location /workspace/coverage/default/1.kmac_long_msg_and_output.1083601446
Short name T405
Test name
Test status
Simulation time 71383401988 ps
CPU time 570.94 seconds
Started Feb 25 01:55:09 PM PST 24
Finished Feb 25 02:04:42 PM PST 24
Peak memory 266164 kb
Host smart-1665624b-f139-4b55-9f02-b316a09a65fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083601446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_an
d_output.1083601446 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/1.kmac_mubi.4178727961
Short name T914
Test name
Test status
Simulation time 14174010511 ps
CPU time 472.85 seconds
Started Feb 25 01:55:30 PM PST 24
Finished Feb 25 02:03:23 PM PST 24
Peak memory 256660 kb
Host smart-12ee7b3d-060f-4243-9477-49d1657f2ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178727961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.4178727961 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mubi/latest


Test location /workspace/coverage/default/1.kmac_sec_cm.1289978313
Short name T107
Test name
Test status
Simulation time 48370844993 ps
CPU time 39.26 seconds
Started Feb 25 01:55:25 PM PST 24
Finished Feb 25 01:56:04 PM PST 24
Peak memory 268704 kb
Host smart-161417a8-8413-4a49-ab4a-00066968eee9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289978313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.1289978313 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/1.kmac_sec_cm/latest


Test location /workspace/coverage/default/1.kmac_sideload.2399987316
Short name T670
Test name
Test status
Simulation time 5672553757 ps
CPU time 179.2 seconds
Started Feb 25 01:55:09 PM PST 24
Finished Feb 25 01:58:10 PM PST 24
Peak memory 243116 kb
Host smart-6c8ccc52-90a2-48ff-a1d9-215c483dd448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399987316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.2399987316 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_sideload/latest


Test location /workspace/coverage/default/1.kmac_smoke.3510357934
Short name T822
Test name
Test status
Simulation time 3047868365 ps
CPU time 61.5 seconds
Started Feb 25 01:55:18 PM PST 24
Finished Feb 25 01:56:20 PM PST 24
Peak memory 223616 kb
Host smart-8034c880-b395-4297-b701-f86f72c80bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510357934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.3510357934 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_smoke/latest


Test location /workspace/coverage/default/1.kmac_stress_all.132386004
Short name T561
Test name
Test status
Simulation time 42428059748 ps
CPU time 496.18 seconds
Started Feb 25 01:55:18 PM PST 24
Finished Feb 25 02:03:35 PM PST 24
Peak memory 273764 kb
Host smart-2a872f75-1684-4ed3-b241-1ac122a39b8a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=132386004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.132386004 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_stress_all/latest


Test location /workspace/coverage/default/1.kmac_test_vectors_kmac.3215473076
Short name T200
Test name
Test status
Simulation time 221161122 ps
CPU time 5.98 seconds
Started Feb 25 01:55:19 PM PST 24
Finished Feb 25 01:55:25 PM PST 24
Peak memory 218428 kb
Host smart-36a129a7-3ec7-41c2-bf1b-4075cef85543
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215473076 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.kmac_test_vectors_kmac.3215473076 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/1.kmac_test_vectors_kmac_xof.554790080
Short name T512
Test name
Test status
Simulation time 203249023 ps
CPU time 6.28 seconds
Started Feb 25 01:55:17 PM PST 24
Finished Feb 25 01:55:24 PM PST 24
Peak memory 219804 kb
Host smart-c0028251-f13e-4572-903f-6eb21b406481
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554790080 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.kmac_test_vectors_kmac_xof.554790080 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_224.967302665
Short name T478
Test name
Test status
Simulation time 62678855515 ps
CPU time 1932.12 seconds
Started Feb 25 01:55:17 PM PST 24
Finished Feb 25 02:27:30 PM PST 24
Peak memory 394240 kb
Host smart-0ba9361b-06f3-4d85-bdae-ce7af2b6c561
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=967302665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.967302665 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_256.3030037217
Short name T536
Test name
Test status
Simulation time 80545323122 ps
CPU time 2023.26 seconds
Started Feb 25 01:55:17 PM PST 24
Finished Feb 25 02:29:01 PM PST 24
Peak memory 387476 kb
Host smart-d52e77a0-b98c-4176-bee4-0ca923a9a0b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3030037217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.3030037217 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_384.840882909
Short name T813
Test name
Test status
Simulation time 15139330013 ps
CPU time 1579.25 seconds
Started Feb 25 01:55:27 PM PST 24
Finished Feb 25 02:21:47 PM PST 24
Peak memory 342240 kb
Host smart-a5db28aa-4309-4709-9421-ff9acf5e2aa5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=840882909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.840882909 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_512.2688835803
Short name T278
Test name
Test status
Simulation time 101430249697 ps
CPU time 1471.24 seconds
Started Feb 25 01:55:20 PM PST 24
Finished Feb 25 02:19:51 PM PST 24
Peak memory 304256 kb
Host smart-0002bfa7-2337-454a-99fa-9a237a4609c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2688835803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.2688835803 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/1.kmac_test_vectors_shake_128.661713339
Short name T1046
Test name
Test status
Simulation time 63583738638 ps
CPU time 4841.43 seconds
Started Feb 25 01:55:18 PM PST 24
Finished Feb 25 03:16:00 PM PST 24
Peak memory 674744 kb
Host smart-3536da33-64b9-4058-844b-b34062a4302f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=661713339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.661713339 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/1.kmac_test_vectors_shake_256.3536159856
Short name T694
Test name
Test status
Simulation time 66558141262 ps
CPU time 4203.18 seconds
Started Feb 25 01:55:17 PM PST 24
Finished Feb 25 03:05:21 PM PST 24
Peak memory 566468 kb
Host smart-33428478-c81e-4faf-aef4-ec86946ec8e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3536159856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.3536159856 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/10.kmac_alert_test.993045535
Short name T590
Test name
Test status
Simulation time 30043947 ps
CPU time 0.85 seconds
Started Feb 25 01:56:15 PM PST 24
Finished Feb 25 01:56:16 PM PST 24
Peak memory 218196 kb
Host smart-a25ef140-488e-4740-a733-0be3e71d6356
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993045535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.993045535 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/10.kmac_alert_test/latest


Test location /workspace/coverage/default/10.kmac_app.3828479573
Short name T159
Test name
Test status
Simulation time 12176381464 ps
CPU time 359.39 seconds
Started Feb 25 01:56:16 PM PST 24
Finished Feb 25 02:02:16 PM PST 24
Peak memory 250280 kb
Host smart-f9a334a1-50b7-49df-8d14-91dc71e6b645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828479573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.3828479573 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_app/latest


Test location /workspace/coverage/default/10.kmac_burst_write.684141685
Short name T642
Test name
Test status
Simulation time 26251704568 ps
CPU time 679.59 seconds
Started Feb 25 01:56:15 PM PST 24
Finished Feb 25 02:07:34 PM PST 24
Peak memory 243008 kb
Host smart-20836e48-dbc2-42d0-ba11-210419a6c8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684141685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.684141685 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_burst_write/latest


Test location /workspace/coverage/default/10.kmac_edn_timeout_error.1283646778
Short name T660
Test name
Test status
Simulation time 170055387 ps
CPU time 11.47 seconds
Started Feb 25 01:56:16 PM PST 24
Finished Feb 25 01:56:28 PM PST 24
Peak memory 227228 kb
Host smart-9b3869f4-0775-4ddc-8c25-6e0d9f7899e0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1283646778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.1283646778 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/10.kmac_entropy_refresh.3260340716
Short name T496
Test name
Test status
Simulation time 11944134095 ps
CPU time 281.26 seconds
Started Feb 25 01:56:18 PM PST 24
Finished Feb 25 02:00:59 PM PST 24
Peak memory 248456 kb
Host smart-1446bcc5-e94b-486c-90b6-37e944efc812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260340716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.3260340716 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/10.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/10.kmac_error.915654637
Short name T762
Test name
Test status
Simulation time 158126468970 ps
CPU time 424.71 seconds
Started Feb 25 01:56:16 PM PST 24
Finished Feb 25 02:03:21 PM PST 24
Peak memory 260020 kb
Host smart-b925d9e5-339a-4890-b070-3bd16b7ac195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915654637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.915654637 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_error/latest


Test location /workspace/coverage/default/10.kmac_key_error.2244006577
Short name T527
Test name
Test status
Simulation time 2276711517 ps
CPU time 6.53 seconds
Started Feb 25 01:56:23 PM PST 24
Finished Feb 25 01:56:30 PM PST 24
Peak memory 218412 kb
Host smart-3f6e2c4c-af85-4151-b1b8-e1f14fb3e3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244006577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.2244006577 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_key_error/latest


Test location /workspace/coverage/default/10.kmac_lc_escalation.484655296
Short name T13
Test name
Test status
Simulation time 92594227 ps
CPU time 1.58 seconds
Started Feb 25 01:56:14 PM PST 24
Finished Feb 25 01:56:16 PM PST 24
Peak memory 219316 kb
Host smart-7e96b0aa-a8c2-413c-a570-6e631a99e4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484655296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.484655296 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/10.kmac_lc_escalation/latest


Test location /workspace/coverage/default/10.kmac_long_msg_and_output.533878197
Short name T586
Test name
Test status
Simulation time 443417164701 ps
CPU time 3064.35 seconds
Started Feb 25 01:56:18 PM PST 24
Finished Feb 25 02:47:23 PM PST 24
Peak memory 444460 kb
Host smart-573273bd-0e4b-44fb-a473-c5910ade7a37
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533878197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_an
d_output.533878197 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/10.kmac_sideload.2575589734
Short name T637
Test name
Test status
Simulation time 69431267354 ps
CPU time 454.04 seconds
Started Feb 25 01:56:16 PM PST 24
Finished Feb 25 02:03:50 PM PST 24
Peak memory 250000 kb
Host smart-93a84177-dddf-4ee9-b05f-a1da5e66d3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575589734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.2575589734 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_sideload/latest


Test location /workspace/coverage/default/10.kmac_smoke.3239741774
Short name T640
Test name
Test status
Simulation time 841569646 ps
CPU time 34.19 seconds
Started Feb 25 01:56:23 PM PST 24
Finished Feb 25 01:56:58 PM PST 24
Peak memory 223864 kb
Host smart-9d62d49d-2efa-401a-a0c0-efb131a757ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239741774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.3239741774 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_smoke/latest


Test location /workspace/coverage/default/10.kmac_stress_all.4264334003
Short name T837
Test name
Test status
Simulation time 26398546825 ps
CPU time 225.54 seconds
Started Feb 25 01:56:14 PM PST 24
Finished Feb 25 02:00:00 PM PST 24
Peak memory 253932 kb
Host smart-9beeceb9-51d3-42ba-8488-29329d0ee126
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4264334003 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.4264334003 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_stress_all/latest


Test location /workspace/coverage/default/10.kmac_test_vectors_kmac.2688683247
Short name T324
Test name
Test status
Simulation time 445537682 ps
CPU time 5.71 seconds
Started Feb 25 01:56:23 PM PST 24
Finished Feb 25 01:56:29 PM PST 24
Peak memory 219028 kb
Host smart-4ea7df30-e4aa-4573-8b42-a62f8e58002b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688683247 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.kmac_test_vectors_kmac.2688683247 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/10.kmac_test_vectors_kmac_xof.1462149233
Short name T949
Test name
Test status
Simulation time 1282565873 ps
CPU time 6.91 seconds
Started Feb 25 01:56:16 PM PST 24
Finished Feb 25 01:56:23 PM PST 24
Peak memory 218292 kb
Host smart-5a3c0a59-342c-49f4-891b-20b294f559af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462149233 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.kmac_test_vectors_kmac_xof.1462149233 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_224.390462310
Short name T353
Test name
Test status
Simulation time 50041940560 ps
CPU time 2173.79 seconds
Started Feb 25 01:56:14 PM PST 24
Finished Feb 25 02:32:29 PM PST 24
Peak memory 403320 kb
Host smart-b9bd35fd-9270-491b-9226-03e83691ee70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=390462310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_224.390462310 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_256.4224573507
Short name T553
Test name
Test status
Simulation time 364562162578 ps
CPU time 2379.75 seconds
Started Feb 25 01:56:17 PM PST 24
Finished Feb 25 02:35:57 PM PST 24
Peak memory 385972 kb
Host smart-bec83664-a529-45ce-9b41-0c3e7839de6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4224573507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_256.4224573507 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_384.2602031400
Short name T483
Test name
Test status
Simulation time 273775470391 ps
CPU time 1800.7 seconds
Started Feb 25 01:56:13 PM PST 24
Finished Feb 25 02:26:14 PM PST 24
Peak memory 335828 kb
Host smart-fe5dbb8e-7706-4a5d-9ef4-4562b7fffeab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2602031400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_384.2602031400 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_512.2140970660
Short name T946
Test name
Test status
Simulation time 139826389534 ps
CPU time 1340.43 seconds
Started Feb 25 01:56:16 PM PST 24
Finished Feb 25 02:18:37 PM PST 24
Peak memory 302396 kb
Host smart-ec54b938-eccb-4c0a-80b6-e20da22754db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2140970660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_512.2140970660 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/10.kmac_test_vectors_shake_128.1577844541
Short name T472
Test name
Test status
Simulation time 1216510613509 ps
CPU time 6215.16 seconds
Started Feb 25 01:56:15 PM PST 24
Finished Feb 25 03:39:52 PM PST 24
Peak memory 670408 kb
Host smart-597efcae-d6ab-4514-b5e1-e6238a4ae26c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1577844541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_128.1577844541 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/10.kmac_test_vectors_shake_256.1278153864
Short name T574
Test name
Test status
Simulation time 111847859992 ps
CPU time 4293.45 seconds
Started Feb 25 01:56:15 PM PST 24
Finished Feb 25 03:07:49 PM PST 24
Peak memory 563964 kb
Host smart-ada78c01-6920-47bf-a13b-f14c8cdea1af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1278153864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_256.1278153864 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/11.kmac_alert_test.1461080936
Short name T312
Test name
Test status
Simulation time 34614887 ps
CPU time 0.9 seconds
Started Feb 25 01:56:27 PM PST 24
Finished Feb 25 01:56:29 PM PST 24
Peak memory 219428 kb
Host smart-a66b1b82-bdac-45e5-9e49-4dec405a42dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461080936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.1461080936 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_alert_test/latest


Test location /workspace/coverage/default/11.kmac_app.3270505890
Short name T850
Test name
Test status
Simulation time 54852712359 ps
CPU time 411.12 seconds
Started Feb 25 01:56:26 PM PST 24
Finished Feb 25 02:03:17 PM PST 24
Peak memory 251280 kb
Host smart-a2a94080-86d3-4f8c-828b-2131b390c92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270505890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.3270505890 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_app/latest


Test location /workspace/coverage/default/11.kmac_burst_write.869650031
Short name T548
Test name
Test status
Simulation time 6146987792 ps
CPU time 207.82 seconds
Started Feb 25 01:56:26 PM PST 24
Finished Feb 25 01:59:54 PM PST 24
Peak memory 229320 kb
Host smart-1b8b7a12-0327-45a5-93ef-88621cd2cf35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869650031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.869650031 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_burst_write/latest


Test location /workspace/coverage/default/11.kmac_entropy_mode_error.3628917394
Short name T870
Test name
Test status
Simulation time 94420949 ps
CPU time 1.28 seconds
Started Feb 25 01:56:28 PM PST 24
Finished Feb 25 01:56:29 PM PST 24
Peak memory 218280 kb
Host smart-fec04f76-59f0-4260-9fc7-8dbb3cdf189a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3628917394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.3628917394 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/11.kmac_entropy_refresh.1303561032
Short name T328
Test name
Test status
Simulation time 126398643307 ps
CPU time 396.34 seconds
Started Feb 25 01:56:31 PM PST 24
Finished Feb 25 02:03:09 PM PST 24
Peak memory 254772 kb
Host smart-2978cb02-9881-43d3-bce4-574157d97a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303561032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.1303561032 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/11.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/11.kmac_error.1337288850
Short name T1011
Test name
Test status
Simulation time 1362096885 ps
CPU time 59.93 seconds
Started Feb 25 01:56:27 PM PST 24
Finished Feb 25 01:57:28 PM PST 24
Peak memory 242944 kb
Host smart-1cd1d854-d8d6-448b-97c1-a1ed91532e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337288850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.1337288850 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_error/latest


Test location /workspace/coverage/default/11.kmac_key_error.2259773626
Short name T867
Test name
Test status
Simulation time 1769168589 ps
CPU time 5.44 seconds
Started Feb 25 01:56:26 PM PST 24
Finished Feb 25 01:56:32 PM PST 24
Peak memory 218276 kb
Host smart-e54ca706-55cb-43ff-b87e-3ccf37b9ac25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259773626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.2259773626 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_key_error/latest


Test location /workspace/coverage/default/11.kmac_long_msg_and_output.1734163877
Short name T252
Test name
Test status
Simulation time 328988472415 ps
CPU time 2232.64 seconds
Started Feb 25 01:56:18 PM PST 24
Finished Feb 25 02:33:31 PM PST 24
Peak memory 389384 kb
Host smart-1211ca93-6bdd-4d4f-b60a-33a6fc7a2e19
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734163877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_a
nd_output.1734163877 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/11.kmac_sideload.1216408871
Short name T955
Test name
Test status
Simulation time 30309368585 ps
CPU time 237.88 seconds
Started Feb 25 01:56:25 PM PST 24
Finished Feb 25 02:00:23 PM PST 24
Peak memory 242952 kb
Host smart-6235e891-45b6-45d9-906c-7a8288343f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216408871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.1216408871 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_sideload/latest


Test location /workspace/coverage/default/11.kmac_smoke.3392632557
Short name T372
Test name
Test status
Simulation time 608604322 ps
CPU time 15.94 seconds
Started Feb 25 01:56:23 PM PST 24
Finished Feb 25 01:56:40 PM PST 24
Peak memory 225828 kb
Host smart-00f41500-b651-4f4e-aca8-f58c86bf7bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392632557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.3392632557 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_smoke/latest


Test location /workspace/coverage/default/11.kmac_stress_all.593398947
Short name T890
Test name
Test status
Simulation time 30538948616 ps
CPU time 759.63 seconds
Started Feb 25 01:56:24 PM PST 24
Finished Feb 25 02:09:04 PM PST 24
Peak memory 267560 kb
Host smart-c9207425-a487-4e54-8d96-0e860b808343
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=593398947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.593398947 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_stress_all/latest


Test location /workspace/coverage/default/11.kmac_test_vectors_kmac.3403478098
Short name T569
Test name
Test status
Simulation time 544852251 ps
CPU time 6.32 seconds
Started Feb 25 01:56:26 PM PST 24
Finished Feb 25 01:56:32 PM PST 24
Peak memory 219820 kb
Host smart-ebb75820-d6c8-4dff-9110-281744dcde67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403478098 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.kmac_test_vectors_kmac.3403478098 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/11.kmac_test_vectors_kmac_xof.4000237290
Short name T779
Test name
Test status
Simulation time 783243520 ps
CPU time 6.38 seconds
Started Feb 25 01:56:24 PM PST 24
Finished Feb 25 01:56:31 PM PST 24
Peak memory 219828 kb
Host smart-dc0f8a1a-d732-4346-af6d-1c43f5a89e68
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000237290 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.kmac_test_vectors_kmac_xof.4000237290 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_224.989979644
Short name T206
Test name
Test status
Simulation time 261634784328 ps
CPU time 2462.49 seconds
Started Feb 25 01:56:25 PM PST 24
Finished Feb 25 02:37:28 PM PST 24
Peak memory 398600 kb
Host smart-56ad55f4-fc8e-4e29-bfef-71e3fd4b3917
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=989979644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_224.989979644 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_256.1033670154
Short name T725
Test name
Test status
Simulation time 20468134376 ps
CPU time 1794.15 seconds
Started Feb 25 01:56:31 PM PST 24
Finished Feb 25 02:26:27 PM PST 24
Peak memory 390556 kb
Host smart-5f1a2344-d685-48d0-8af5-5eeb30221331
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1033670154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_256.1033670154 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_384.3826135966
Short name T751
Test name
Test status
Simulation time 1228570613522 ps
CPU time 2217.29 seconds
Started Feb 25 01:56:31 PM PST 24
Finished Feb 25 02:33:30 PM PST 24
Peak memory 343176 kb
Host smart-8b979cd8-a675-4c92-a2d6-bbc656d397f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3826135966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_384.3826135966 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_512.4251428819
Short name T110
Test name
Test status
Simulation time 128101128407 ps
CPU time 1331.65 seconds
Started Feb 25 01:56:27 PM PST 24
Finished Feb 25 02:18:39 PM PST 24
Peak memory 303268 kb
Host smart-01db528c-66e4-4fd7-b558-15293b5e8bb8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4251428819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_512.4251428819 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/11.kmac_test_vectors_shake_128.1140991500
Short name T508
Test name
Test status
Simulation time 123759517244 ps
CPU time 5466.86 seconds
Started Feb 25 01:56:28 PM PST 24
Finished Feb 25 03:27:35 PM PST 24
Peak memory 652440 kb
Host smart-6406f336-01b0-441d-baed-b1a592cb7365
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1140991500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_128.1140991500 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/11.kmac_test_vectors_shake_256.489306592
Short name T276
Test name
Test status
Simulation time 211103094552 ps
CPU time 4534.35 seconds
Started Feb 25 01:56:25 PM PST 24
Finished Feb 25 03:12:00 PM PST 24
Peak memory 568936 kb
Host smart-19e00a2b-f0b3-4763-8dd9-322ddfb6c7ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=489306592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_256.489306592 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/12.kmac_app.1447916582
Short name T486
Test name
Test status
Simulation time 3760911780 ps
CPU time 203.09 seconds
Started Feb 25 01:56:35 PM PST 24
Finished Feb 25 01:59:58 PM PST 24
Peak memory 242608 kb
Host smart-d6f77f69-1120-4a35-9084-4380a9f565d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447916582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.1447916582 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_app/latest


Test location /workspace/coverage/default/12.kmac_burst_write.524050822
Short name T693
Test name
Test status
Simulation time 19382051160 ps
CPU time 524.67 seconds
Started Feb 25 01:56:31 PM PST 24
Finished Feb 25 02:05:17 PM PST 24
Peak memory 232724 kb
Host smart-e9ce99a1-cc39-4cc9-bf65-082c68294349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524050822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.524050822 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_burst_write/latest


Test location /workspace/coverage/default/12.kmac_edn_timeout_error.412622937
Short name T106
Test name
Test status
Simulation time 140988963 ps
CPU time 1.29 seconds
Started Feb 25 01:56:34 PM PST 24
Finished Feb 25 01:56:36 PM PST 24
Peak memory 218072 kb
Host smart-807eecb2-2041-410c-9f9d-6752954bf42c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=412622937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.412622937 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/12.kmac_entropy_mode_error.3985107297
Short name T856
Test name
Test status
Simulation time 26495214 ps
CPU time 1.2 seconds
Started Feb 25 01:56:34 PM PST 24
Finished Feb 25 01:56:35 PM PST 24
Peak memory 218272 kb
Host smart-bea017c5-8e9b-4b07-bee4-7cea7f926e9d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3985107297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.3985107297 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/12.kmac_entropy_refresh.3875281677
Short name T744
Test name
Test status
Simulation time 4843607736 ps
CPU time 66.03 seconds
Started Feb 25 01:56:41 PM PST 24
Finished Feb 25 01:57:47 PM PST 24
Peak memory 239616 kb
Host smart-0f761bc3-d9a6-4dd2-8e7d-3e6693e8e924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875281677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.3875281677 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/12.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/12.kmac_error.2914300291
Short name T855
Test name
Test status
Simulation time 3138914372 ps
CPU time 264.26 seconds
Started Feb 25 01:56:34 PM PST 24
Finished Feb 25 02:00:59 PM PST 24
Peak memory 257576 kb
Host smart-9fecd816-679e-480e-b155-36df90b584de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914300291 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.2914300291 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_error/latest


Test location /workspace/coverage/default/12.kmac_key_error.2800359778
Short name T269
Test name
Test status
Simulation time 10552554636 ps
CPU time 8.89 seconds
Started Feb 25 01:56:34 PM PST 24
Finished Feb 25 01:56:43 PM PST 24
Peak memory 218420 kb
Host smart-c51f856e-c00a-4761-9e2d-334e3284c910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800359778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.2800359778 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_key_error/latest


Test location /workspace/coverage/default/12.kmac_lc_escalation.3240736384
Short name T23
Test name
Test status
Simulation time 42939432 ps
CPU time 1.4 seconds
Started Feb 25 01:56:32 PM PST 24
Finished Feb 25 01:56:34 PM PST 24
Peak memory 218252 kb
Host smart-fb189981-8de5-4598-a42f-483a4206d5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240736384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.3240736384 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/12.kmac_lc_escalation/latest


Test location /workspace/coverage/default/12.kmac_long_msg_and_output.1618309415
Short name T226
Test name
Test status
Simulation time 47302637903 ps
CPU time 213.36 seconds
Started Feb 25 01:56:31 PM PST 24
Finished Feb 25 02:00:05 PM PST 24
Peak memory 243004 kb
Host smart-237e703b-3467-417f-8763-e00f48c17d6f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618309415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_a
nd_output.1618309415 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/12.kmac_sideload.1193638794
Short name T860
Test name
Test status
Simulation time 9932976343 ps
CPU time 62.05 seconds
Started Feb 25 01:56:23 PM PST 24
Finished Feb 25 01:57:26 PM PST 24
Peak memory 229648 kb
Host smart-f1aa9630-e4cc-427b-bcc0-0f37a624f9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193638794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.1193638794 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_sideload/latest


Test location /workspace/coverage/default/12.kmac_smoke.2583826222
Short name T242
Test name
Test status
Simulation time 13518372931 ps
CPU time 60.85 seconds
Started Feb 25 01:56:25 PM PST 24
Finished Feb 25 01:57:26 PM PST 24
Peak memory 226528 kb
Host smart-f3ed2289-ee7a-4313-9c33-8725a0ecaea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583826222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.2583826222 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_smoke/latest


Test location /workspace/coverage/default/12.kmac_stress_all.2122586955
Short name T817
Test name
Test status
Simulation time 15787699842 ps
CPU time 212.73 seconds
Started Feb 25 01:56:32 PM PST 24
Finished Feb 25 02:00:06 PM PST 24
Peak memory 272272 kb
Host smart-c1150bfe-2d43-4321-90d4-33c5cadb7408
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2122586955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.2122586955 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_stress_all/latest


Test location /workspace/coverage/default/12.kmac_test_vectors_kmac.4229135225
Short name T379
Test name
Test status
Simulation time 212679948 ps
CPU time 6.59 seconds
Started Feb 25 01:56:25 PM PST 24
Finished Feb 25 01:56:32 PM PST 24
Peak memory 219696 kb
Host smart-a60ae348-9d86-4072-9627-a7e615b10e8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229135225 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.kmac_test_vectors_kmac.4229135225 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/12.kmac_test_vectors_kmac_xof.139313823
Short name T591
Test name
Test status
Simulation time 886005211 ps
CPU time 6.15 seconds
Started Feb 25 01:56:31 PM PST 24
Finished Feb 25 01:56:39 PM PST 24
Peak memory 218408 kb
Host smart-185e4fc4-8c86-4414-9f02-cbf69ab70756
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139313823 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.kmac_test_vectors_kmac_xof.139313823 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_224.3424833204
Short name T262
Test name
Test status
Simulation time 99829748474 ps
CPU time 2622.56 seconds
Started Feb 25 01:56:32 PM PST 24
Finished Feb 25 02:40:16 PM PST 24
Peak memory 397648 kb
Host smart-62e1d650-cd39-497f-ae1f-6d8a125f9898
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3424833204 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_224.3424833204 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_256.3484809387
Short name T11
Test name
Test status
Simulation time 36966349669 ps
CPU time 1931.77 seconds
Started Feb 25 01:56:31 PM PST 24
Finished Feb 25 02:28:45 PM PST 24
Peak memory 377484 kb
Host smart-72b24dcc-0e35-4adf-890e-84d6ca52513a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3484809387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_256.3484809387 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_384.2409921453
Short name T566
Test name
Test status
Simulation time 15194309267 ps
CPU time 1629.9 seconds
Started Feb 25 01:56:29 PM PST 24
Finished Feb 25 02:23:39 PM PST 24
Peak memory 337328 kb
Host smart-cde1495d-2250-429d-81d0-4261c7fd5e3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2409921453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_384.2409921453 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_512.2891133972
Short name T229
Test name
Test status
Simulation time 42648655151 ps
CPU time 1348.86 seconds
Started Feb 25 01:56:25 PM PST 24
Finished Feb 25 02:18:54 PM PST 24
Peak memory 300616 kb
Host smart-3e60f08e-7e76-4581-b534-d6ba96b21aa7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2891133972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_512.2891133972 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/12.kmac_test_vectors_shake_128.965901894
Short name T510
Test name
Test status
Simulation time 185595780967 ps
CPU time 5751.64 seconds
Started Feb 25 01:56:27 PM PST 24
Finished Feb 25 03:32:20 PM PST 24
Peak memory 656516 kb
Host smart-f7f3c24b-1736-4e23-8db6-b56cbae28317
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=965901894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_128.965901894 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/12.kmac_test_vectors_shake_256.1133934751
Short name T528
Test name
Test status
Simulation time 195650052661 ps
CPU time 4789.2 seconds
Started Feb 25 01:56:23 PM PST 24
Finished Feb 25 03:16:12 PM PST 24
Peak memory 579336 kb
Host smart-df587b4b-8384-4d89-8ded-e173e8c6f16d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1133934751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_256.1133934751 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/13.kmac_alert_test.3341368812
Short name T985
Test name
Test status
Simulation time 15757644 ps
CPU time 0.83 seconds
Started Feb 25 01:56:42 PM PST 24
Finished Feb 25 01:56:43 PM PST 24
Peak memory 219304 kb
Host smart-9e599768-0991-431d-a168-3b7a89c3e3d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341368812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.3341368812 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_alert_test/latest


Test location /workspace/coverage/default/13.kmac_app.1999220985
Short name T749
Test name
Test status
Simulation time 16641827674 ps
CPU time 354.19 seconds
Started Feb 25 01:56:30 PM PST 24
Finished Feb 25 02:02:26 PM PST 24
Peak memory 248512 kb
Host smart-08f3ecd1-9dee-4565-96cf-35f1813adf6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999220985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.1999220985 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_app/latest


Test location /workspace/coverage/default/13.kmac_burst_write.1855839589
Short name T567
Test name
Test status
Simulation time 66767519760 ps
CPU time 978.64 seconds
Started Feb 25 01:56:35 PM PST 24
Finished Feb 25 02:12:54 PM PST 24
Peak memory 236512 kb
Host smart-fed40ad7-9967-4ae8-b6dc-dbc9c2fe9034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855839589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.1855839589 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_burst_write/latest


Test location /workspace/coverage/default/13.kmac_edn_timeout_error.4243911440
Short name T543
Test name
Test status
Simulation time 784862016 ps
CPU time 15.34 seconds
Started Feb 25 01:56:41 PM PST 24
Finished Feb 25 01:56:57 PM PST 24
Peak memory 223272 kb
Host smart-be2c2af7-2997-4a57-bb12-912e7e462120
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4243911440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.4243911440 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/13.kmac_entropy_mode_error.478271365
Short name T429
Test name
Test status
Simulation time 54565514 ps
CPU time 0.97 seconds
Started Feb 25 01:56:44 PM PST 24
Finished Feb 25 01:56:45 PM PST 24
Peak memory 218284 kb
Host smart-2271d89c-471a-48e9-837b-eb48e431bed5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=478271365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.478271365 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/13.kmac_entropy_refresh.2589412145
Short name T772
Test name
Test status
Simulation time 9354888935 ps
CPU time 377.46 seconds
Started Feb 25 01:56:34 PM PST 24
Finished Feb 25 02:02:51 PM PST 24
Peak memory 250832 kb
Host smart-8e353bce-6955-492e-92d3-26c4e32b77c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589412145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.2589412145 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/13.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/13.kmac_error.3198432592
Short name T891
Test name
Test status
Simulation time 5881501220 ps
CPU time 96.54 seconds
Started Feb 25 01:56:42 PM PST 24
Finished Feb 25 01:58:20 PM PST 24
Peak memory 242928 kb
Host smart-354610bc-0607-4f93-be5c-18e894707288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198432592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.3198432592 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_error/latest


Test location /workspace/coverage/default/13.kmac_key_error.1446302769
Short name T884
Test name
Test status
Simulation time 1925203822 ps
CPU time 2.93 seconds
Started Feb 25 01:56:45 PM PST 24
Finished Feb 25 01:56:48 PM PST 24
Peak memory 218376 kb
Host smart-6b6c3b8c-fb64-4d2e-b573-22e40834592d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446302769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.1446302769 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_key_error/latest


Test location /workspace/coverage/default/13.kmac_lc_escalation.4107586148
Short name T918
Test name
Test status
Simulation time 51483251 ps
CPU time 1.36 seconds
Started Feb 25 01:56:40 PM PST 24
Finished Feb 25 01:56:42 PM PST 24
Peak memory 219348 kb
Host smart-b6ab5cfa-3195-4849-8ebc-7dae0e57088f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107586148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.4107586148 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/13.kmac_lc_escalation/latest


Test location /workspace/coverage/default/13.kmac_long_msg_and_output.657513682
Short name T295
Test name
Test status
Simulation time 41232305997 ps
CPU time 1561.77 seconds
Started Feb 25 01:56:34 PM PST 24
Finished Feb 25 02:22:36 PM PST 24
Peak memory 342952 kb
Host smart-c485b6a7-23e6-4df4-8063-ace7ff0239ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657513682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_an
d_output.657513682 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/13.kmac_sideload.261127148
Short name T1041
Test name
Test status
Simulation time 2510227256 ps
CPU time 178.92 seconds
Started Feb 25 01:56:34 PM PST 24
Finished Feb 25 01:59:33 PM PST 24
Peak memory 238652 kb
Host smart-5cdfe0f1-c786-42b4-ab85-e834e3fc3f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261127148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.261127148 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_sideload/latest


Test location /workspace/coverage/default/13.kmac_stress_all.503047179
Short name T426
Test name
Test status
Simulation time 105384537114 ps
CPU time 2890.8 seconds
Started Feb 25 01:56:43 PM PST 24
Finished Feb 25 02:44:54 PM PST 24
Peak memory 472572 kb
Host smart-990dc229-46d5-4c05-9352-18797df51ba3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=503047179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.503047179 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_stress_all/latest


Test location /workspace/coverage/default/13.kmac_stress_all_with_rand_reset.780290330
Short name T966
Test name
Test status
Simulation time 11117082914 ps
CPU time 386.04 seconds
Started Feb 25 01:56:45 PM PST 24
Finished Feb 25 02:03:11 PM PST 24
Peak memory 276076 kb
Host smart-431aec79-d7fc-4a7f-94a8-37ac9a88f419
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=780290330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all_with_rand_reset.780290330 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/13.kmac_test_vectors_kmac.1537808644
Short name T863
Test name
Test status
Simulation time 137967400 ps
CPU time 5.81 seconds
Started Feb 25 01:56:34 PM PST 24
Finished Feb 25 01:56:40 PM PST 24
Peak memory 218400 kb
Host smart-eb85bf96-7bb3-41e0-8aac-f06e1a9ce23a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537808644 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.kmac_test_vectors_kmac.1537808644 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/13.kmac_test_vectors_kmac_xof.1703061857
Short name T600
Test name
Test status
Simulation time 115771117 ps
CPU time 6.95 seconds
Started Feb 25 01:56:30 PM PST 24
Finished Feb 25 01:56:37 PM PST 24
Peak memory 218440 kb
Host smart-f39d77d7-ea40-46c6-bd8f-cf433aa62117
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703061857 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.kmac_test_vectors_kmac_xof.1703061857 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_224.2219595817
Short name T397
Test name
Test status
Simulation time 42070269565 ps
CPU time 2256.45 seconds
Started Feb 25 01:56:34 PM PST 24
Finished Feb 25 02:34:10 PM PST 24
Peak memory 393820 kb
Host smart-4b114f90-fe0d-45f6-acb0-b73e6520c4f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2219595817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_224.2219595817 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_256.341964991
Short name T757
Test name
Test status
Simulation time 40050342466 ps
CPU time 2017.58 seconds
Started Feb 25 01:56:34 PM PST 24
Finished Feb 25 02:30:12 PM PST 24
Peak memory 388660 kb
Host smart-0f3757c5-47a4-41ba-bcdd-20bb19ea026d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=341964991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_256.341964991 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_384.410205867
Short name T958
Test name
Test status
Simulation time 15821207231 ps
CPU time 1751.48 seconds
Started Feb 25 01:56:30 PM PST 24
Finished Feb 25 02:25:44 PM PST 24
Peak memory 347640 kb
Host smart-e767b1d5-e806-4d3d-8cc8-5da9a29ffdac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=410205867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_384.410205867 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_512.1805639513
Short name T231
Test name
Test status
Simulation time 200347014922 ps
CPU time 1367.5 seconds
Started Feb 25 01:56:34 PM PST 24
Finished Feb 25 02:19:22 PM PST 24
Peak memory 298156 kb
Host smart-0a834541-2584-4165-85ff-e48c1234087e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1805639513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_512.1805639513 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/13.kmac_test_vectors_shake_128.3892823679
Short name T1052
Test name
Test status
Simulation time 320249092710 ps
CPU time 5132.98 seconds
Started Feb 25 01:56:32 PM PST 24
Finished Feb 25 03:22:07 PM PST 24
Peak memory 649912 kb
Host smart-64637fdb-8fe3-4712-a5e2-37adbd0b2adc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3892823679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_128.3892823679 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/13.kmac_test_vectors_shake_256.3690433429
Short name T327
Test name
Test status
Simulation time 829456870028 ps
CPU time 4927.06 seconds
Started Feb 25 01:56:30 PM PST 24
Finished Feb 25 03:18:38 PM PST 24
Peak memory 572740 kb
Host smart-1e781117-3fe8-429a-a575-2c3c45cbbc1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3690433429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_256.3690433429 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/14.kmac_alert_test.1501087321
Short name T474
Test name
Test status
Simulation time 21665315 ps
CPU time 0.83 seconds
Started Feb 25 01:56:42 PM PST 24
Finished Feb 25 01:56:44 PM PST 24
Peak memory 218068 kb
Host smart-29bf2d8f-cf27-4ee3-94bc-ef07c090b227
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501087321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.1501087321 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_alert_test/latest


Test location /workspace/coverage/default/14.kmac_app.2418403420
Short name T876
Test name
Test status
Simulation time 118667453660 ps
CPU time 266.69 seconds
Started Feb 25 01:56:49 PM PST 24
Finished Feb 25 02:01:16 PM PST 24
Peak memory 246688 kb
Host smart-a000faad-8980-4236-869b-a1882e687c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418403420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.2418403420 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_app/latest


Test location /workspace/coverage/default/14.kmac_burst_write.129025864
Short name T293
Test name
Test status
Simulation time 91924884364 ps
CPU time 1171.1 seconds
Started Feb 25 01:56:42 PM PST 24
Finished Feb 25 02:16:14 PM PST 24
Peak memory 243136 kb
Host smart-caabaaba-3a59-46ff-8d50-9a0d46abb0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129025864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.129025864 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_burst_write/latest


Test location /workspace/coverage/default/14.kmac_edn_timeout_error.3187094655
Short name T470
Test name
Test status
Simulation time 129868801 ps
CPU time 3.84 seconds
Started Feb 25 01:56:48 PM PST 24
Finished Feb 25 01:56:52 PM PST 24
Peak memory 220756 kb
Host smart-aca64e16-1bbe-4209-8458-885e2811d929
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3187094655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.3187094655 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/14.kmac_entropy_mode_error.3319157426
Short name T560
Test name
Test status
Simulation time 134107024 ps
CPU time 1.18 seconds
Started Feb 25 01:56:41 PM PST 24
Finished Feb 25 01:56:43 PM PST 24
Peak memory 218200 kb
Host smart-b329631f-0625-4835-90a7-3bf69fa48a96
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3319157426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.3319157426 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/14.kmac_entropy_refresh.1644460019
Short name T653
Test name
Test status
Simulation time 13496416386 ps
CPU time 184.14 seconds
Started Feb 25 01:56:41 PM PST 24
Finished Feb 25 01:59:45 PM PST 24
Peak memory 238676 kb
Host smart-f403d342-b60e-4fdd-a54e-eadc37a96501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644460019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.1644460019 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/14.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/14.kmac_error.1513560267
Short name T167
Test name
Test status
Simulation time 3776783213 ps
CPU time 151.23 seconds
Started Feb 25 01:56:44 PM PST 24
Finished Feb 25 01:59:16 PM PST 24
Peak memory 251252 kb
Host smart-d5608763-4868-4de0-ac69-fc28577a4a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513560267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.1513560267 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_error/latest


Test location /workspace/coverage/default/14.kmac_key_error.1839628030
Short name T410
Test name
Test status
Simulation time 955781733 ps
CPU time 6.04 seconds
Started Feb 25 01:56:44 PM PST 24
Finished Feb 25 01:56:51 PM PST 24
Peak memory 218284 kb
Host smart-1be04fc9-4e19-401a-befc-973b40196a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839628030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.1839628030 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_key_error/latest


Test location /workspace/coverage/default/14.kmac_lc_escalation.2254160977
Short name T86
Test name
Test status
Simulation time 106122306 ps
CPU time 1.18 seconds
Started Feb 25 01:56:46 PM PST 24
Finished Feb 25 01:56:47 PM PST 24
Peak memory 219400 kb
Host smart-455b9258-ba7f-4f06-9593-74d049237bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254160977 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.2254160977 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/14.kmac_lc_escalation/latest


Test location /workspace/coverage/default/14.kmac_long_msg_and_output.2242586667
Short name T237
Test name
Test status
Simulation time 68065990857 ps
CPU time 2372.24 seconds
Started Feb 25 01:56:42 PM PST 24
Finished Feb 25 02:36:15 PM PST 24
Peak memory 418120 kb
Host smart-f6bdc374-03a3-4041-8bdb-dc8019af6c5e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242586667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_a
nd_output.2242586667 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/14.kmac_sideload.3272008841
Short name T790
Test name
Test status
Simulation time 5806981058 ps
CPU time 544.58 seconds
Started Feb 25 01:56:46 PM PST 24
Finished Feb 25 02:05:51 PM PST 24
Peak memory 254848 kb
Host smart-0768adfb-d780-449a-8503-c6e9af514c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272008841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.3272008841 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_sideload/latest


Test location /workspace/coverage/default/14.kmac_smoke.3130149226
Short name T533
Test name
Test status
Simulation time 1403821873 ps
CPU time 39.53 seconds
Started Feb 25 01:56:45 PM PST 24
Finished Feb 25 01:57:24 PM PST 24
Peak memory 223628 kb
Host smart-4dc17702-0a7c-40d9-9c29-95ad9affd4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130149226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.3130149226 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_smoke/latest


Test location /workspace/coverage/default/14.kmac_stress_all.1475255592
Short name T807
Test name
Test status
Simulation time 45821363521 ps
CPU time 1136.42 seconds
Started Feb 25 01:56:41 PM PST 24
Finished Feb 25 02:15:38 PM PST 24
Peak memory 354448 kb
Host smart-73f7375b-141c-4630-a311-88446ed5d33c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1475255592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.1475255592 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_stress_all/latest


Test location /workspace/coverage/default/14.kmac_test_vectors_kmac.1193047100
Short name T463
Test name
Test status
Simulation time 297384930 ps
CPU time 6.45 seconds
Started Feb 25 01:56:45 PM PST 24
Finished Feb 25 01:56:51 PM PST 24
Peak memory 219724 kb
Host smart-08590598-884f-46fe-8250-d1bc5b279a8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193047100 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.kmac_test_vectors_kmac.1193047100 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/14.kmac_test_vectors_kmac_xof.3509445286
Short name T839
Test name
Test status
Simulation time 264247086 ps
CPU time 6.75 seconds
Started Feb 25 01:56:42 PM PST 24
Finished Feb 25 01:56:49 PM PST 24
Peak memory 218368 kb
Host smart-d2080ae4-14ed-473a-83b8-e528d9750c8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509445286 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.kmac_test_vectors_kmac_xof.3509445286 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_224.882452304
Short name T797
Test name
Test status
Simulation time 194338182226 ps
CPU time 2426.85 seconds
Started Feb 25 01:56:48 PM PST 24
Finished Feb 25 02:37:15 PM PST 24
Peak memory 389956 kb
Host smart-787a5a58-7f87-4e8b-8924-44a9e55a7185
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=882452304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_224.882452304 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_256.2719989849
Short name T479
Test name
Test status
Simulation time 79709522208 ps
CPU time 1886.18 seconds
Started Feb 25 01:56:45 PM PST 24
Finished Feb 25 02:28:11 PM PST 24
Peak memory 388432 kb
Host smart-d3558bd7-c767-425d-8ef6-27c3a9e8a243
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2719989849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_256.2719989849 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_384.455002034
Short name T680
Test name
Test status
Simulation time 16172506402 ps
CPU time 1664.92 seconds
Started Feb 25 01:56:44 PM PST 24
Finished Feb 25 02:24:29 PM PST 24
Peak memory 344144 kb
Host smart-a9e25ebd-ec1c-4dd8-a33b-7b947619f2a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=455002034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_384.455002034 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_512.2596630226
Short name T835
Test name
Test status
Simulation time 723817816673 ps
CPU time 1615.53 seconds
Started Feb 25 01:56:41 PM PST 24
Finished Feb 25 02:23:37 PM PST 24
Peak memory 307864 kb
Host smart-a76cad97-522a-4581-aa94-397ac3cf1e42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2596630226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_512.2596630226 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/14.kmac_test_vectors_shake_128.772479294
Short name T905
Test name
Test status
Simulation time 708268489642 ps
CPU time 6194.11 seconds
Started Feb 25 01:56:45 PM PST 24
Finished Feb 25 03:39:59 PM PST 24
Peak memory 649996 kb
Host smart-dc4053b1-e999-4fb3-9867-5ab0770207d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=772479294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_128.772479294 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/14.kmac_test_vectors_shake_256.1645139682
Short name T812
Test name
Test status
Simulation time 2744095856012 ps
CPU time 5878.95 seconds
Started Feb 25 01:56:42 PM PST 24
Finished Feb 25 03:34:43 PM PST 24
Peak memory 560588 kb
Host smart-476b9893-2141-40e8-9b0e-6f849a21f164
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1645139682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_256.1645139682 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/15.kmac_alert_test.2570816496
Short name T380
Test name
Test status
Simulation time 25262163 ps
CPU time 0.83 seconds
Started Feb 25 01:56:51 PM PST 24
Finished Feb 25 01:56:52 PM PST 24
Peak memory 219312 kb
Host smart-a33d86fa-068a-4eff-9832-3aea8f33eee8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570816496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.2570816496 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_alert_test/latest


Test location /workspace/coverage/default/15.kmac_app.2475743524
Short name T420
Test name
Test status
Simulation time 4106677583 ps
CPU time 91.11 seconds
Started Feb 25 01:56:57 PM PST 24
Finished Feb 25 01:58:28 PM PST 24
Peak memory 234360 kb
Host smart-e7c24785-9cda-4d78-9fdf-bbdb227f02c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475743524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.2475743524 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_app/latest


Test location /workspace/coverage/default/15.kmac_burst_write.1656047798
Short name T695
Test name
Test status
Simulation time 6197647057 ps
CPU time 550.78 seconds
Started Feb 25 01:56:49 PM PST 24
Finished Feb 25 02:06:00 PM PST 24
Peak memory 234744 kb
Host smart-1b873d09-4e30-4994-9467-4d78418f1112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656047798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.1656047798 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_burst_write/latest


Test location /workspace/coverage/default/15.kmac_edn_timeout_error.2538874852
Short name T465
Test name
Test status
Simulation time 27242539 ps
CPU time 0.87 seconds
Started Feb 25 01:56:51 PM PST 24
Finished Feb 25 01:56:52 PM PST 24
Peak memory 218156 kb
Host smart-51298c76-23e1-42b9-a06b-9af7f8a0ee1d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2538874852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.2538874852 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/15.kmac_entropy_mode_error.1695009037
Short name T493
Test name
Test status
Simulation time 34298582 ps
CPU time 1.09 seconds
Started Feb 25 01:56:49 PM PST 24
Finished Feb 25 01:56:51 PM PST 24
Peak memory 218268 kb
Host smart-ad9ed111-1af1-45c1-91e2-9a169c215097
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1695009037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.1695009037 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/15.kmac_entropy_refresh.514350200
Short name T417
Test name
Test status
Simulation time 15273869343 ps
CPU time 216.35 seconds
Started Feb 25 01:56:50 PM PST 24
Finished Feb 25 02:00:27 PM PST 24
Peak memory 241972 kb
Host smart-0f45b624-bb7f-4e79-8a44-863c1de948b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514350200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.514350200 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/15.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/15.kmac_error.228078007
Short name T564
Test name
Test status
Simulation time 67865188932 ps
CPU time 481.27 seconds
Started Feb 25 01:56:50 PM PST 24
Finished Feb 25 02:04:52 PM PST 24
Peak memory 267476 kb
Host smart-eb9efe2c-040b-406c-9ea2-f5bee62cdd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228078007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.228078007 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_error/latest


Test location /workspace/coverage/default/15.kmac_key_error.2722100297
Short name T1054
Test name
Test status
Simulation time 453189770 ps
CPU time 3.5 seconds
Started Feb 25 01:56:55 PM PST 24
Finished Feb 25 01:56:58 PM PST 24
Peak memory 218296 kb
Host smart-03e2db5f-7b1a-4bd8-bfcd-c1393cf52d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722100297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.2722100297 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_key_error/latest


Test location /workspace/coverage/default/15.kmac_lc_escalation.1915768378
Short name T607
Test name
Test status
Simulation time 76747101 ps
CPU time 1.47 seconds
Started Feb 25 01:56:52 PM PST 24
Finished Feb 25 01:56:53 PM PST 24
Peak memory 219296 kb
Host smart-c63d8500-4f31-4e11-af03-924476d92e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915768378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.1915768378 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/15.kmac_lc_escalation/latest


Test location /workspace/coverage/default/15.kmac_long_msg_and_output.2188619344
Short name T509
Test name
Test status
Simulation time 44648105509 ps
CPU time 2631.82 seconds
Started Feb 25 01:56:51 PM PST 24
Finished Feb 25 02:40:43 PM PST 24
Peak memory 428264 kb
Host smart-01be04c0-d57e-4545-8207-85c39928a6e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188619344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_a
nd_output.2188619344 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/15.kmac_sideload.2882733184
Short name T459
Test name
Test status
Simulation time 61358217830 ps
CPU time 268.77 seconds
Started Feb 25 01:56:51 PM PST 24
Finished Feb 25 02:01:19 PM PST 24
Peak memory 245784 kb
Host smart-dc7220f9-a05c-41fb-982c-8aecb4f5aeca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882733184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.2882733184 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_sideload/latest


Test location /workspace/coverage/default/15.kmac_smoke.3521665045
Short name T1004
Test name
Test status
Simulation time 4772228494 ps
CPU time 32.11 seconds
Started Feb 25 01:56:44 PM PST 24
Finished Feb 25 01:57:16 PM PST 24
Peak memory 223444 kb
Host smart-fded06c1-45fa-410d-b5c5-6333d89766a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521665045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.3521665045 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_smoke/latest


Test location /workspace/coverage/default/15.kmac_stress_all.2486852460
Short name T505
Test name
Test status
Simulation time 79193856959 ps
CPU time 1759.5 seconds
Started Feb 25 01:56:48 PM PST 24
Finished Feb 25 02:26:09 PM PST 24
Peak memory 380348 kb
Host smart-5d09d68d-d187-4e19-866c-2d73b2ccfb41
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2486852460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.2486852460 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_stress_all/latest


Test location /workspace/coverage/default/15.kmac_test_vectors_kmac.4128921899
Short name T244
Test name
Test status
Simulation time 396897798 ps
CPU time 5.92 seconds
Started Feb 25 01:56:51 PM PST 24
Finished Feb 25 01:56:57 PM PST 24
Peak memory 218368 kb
Host smart-1ca5495b-35ed-49ba-82a5-1c9450102b1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128921899 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.kmac_test_vectors_kmac.4128921899 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/15.kmac_test_vectors_kmac_xof.455722027
Short name T829
Test name
Test status
Simulation time 182094325 ps
CPU time 5.69 seconds
Started Feb 25 01:56:50 PM PST 24
Finished Feb 25 01:56:56 PM PST 24
Peak memory 219524 kb
Host smart-d9b8010d-e43a-4fda-a77a-feefe450143c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455722027 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.kmac_test_vectors_kmac_xof.455722027 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_224.3306435376
Short name T841
Test name
Test status
Simulation time 20787659692 ps
CPU time 2011.36 seconds
Started Feb 25 01:56:51 PM PST 24
Finished Feb 25 02:30:23 PM PST 24
Peak memory 397908 kb
Host smart-4937f90f-f858-4d23-ac4e-7b7f54d773f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3306435376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_224.3306435376 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_256.2292167139
Short name T221
Test name
Test status
Simulation time 62286208431 ps
CPU time 1873.04 seconds
Started Feb 25 01:56:57 PM PST 24
Finished Feb 25 02:28:10 PM PST 24
Peak memory 379752 kb
Host smart-f3e59c61-6d5e-4baf-8fe3-fb31a8d34b10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2292167139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_256.2292167139 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_384.4192299316
Short name T266
Test name
Test status
Simulation time 58371228832 ps
CPU time 1554.7 seconds
Started Feb 25 01:56:50 PM PST 24
Finished Feb 25 02:22:45 PM PST 24
Peak memory 343208 kb
Host smart-c3b9fe78-9431-426c-9e10-1b947b795bfc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4192299316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_384.4192299316 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_512.2446072678
Short name T198
Test name
Test status
Simulation time 114775615613 ps
CPU time 1464.75 seconds
Started Feb 25 01:56:51 PM PST 24
Finished Feb 25 02:21:16 PM PST 24
Peak memory 302704 kb
Host smart-80bf03e2-62be-438b-b607-d57078c8d008
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2446072678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_512.2446072678 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/15.kmac_test_vectors_shake_128.2331971454
Short name T271
Test name
Test status
Simulation time 123799179063 ps
CPU time 5354.36 seconds
Started Feb 25 01:56:52 PM PST 24
Finished Feb 25 03:26:08 PM PST 24
Peak memory 647740 kb
Host smart-42bcb322-4085-4b07-a436-dc1874bb360e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2331971454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_128.2331971454 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/15.kmac_test_vectors_shake_256.3634774730
Short name T916
Test name
Test status
Simulation time 547927931570 ps
CPU time 5078.79 seconds
Started Feb 25 01:56:52 PM PST 24
Finished Feb 25 03:21:32 PM PST 24
Peak memory 573512 kb
Host smart-a429c26c-3f80-40a0-bfc1-ac4b4595e2e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3634774730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_256.3634774730 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/16.kmac_alert_test.3815625394
Short name T250
Test name
Test status
Simulation time 35475722 ps
CPU time 0.86 seconds
Started Feb 25 01:57:08 PM PST 24
Finished Feb 25 01:57:09 PM PST 24
Peak memory 218084 kb
Host smart-1337d7f3-b524-4ead-a628-5e5c769f15ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815625394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.3815625394 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_alert_test/latest


Test location /workspace/coverage/default/16.kmac_app.1756251059
Short name T1014
Test name
Test status
Simulation time 3098933766 ps
CPU time 122.22 seconds
Started Feb 25 01:57:07 PM PST 24
Finished Feb 25 01:59:09 PM PST 24
Peak memory 242924 kb
Host smart-169c5dd0-f33e-4f78-9985-526d90b3677e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756251059 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.1756251059 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_app/latest


Test location /workspace/coverage/default/16.kmac_burst_write.2550340915
Short name T147
Test name
Test status
Simulation time 49138661038 ps
CPU time 410.8 seconds
Started Feb 25 01:57:05 PM PST 24
Finished Feb 25 02:03:57 PM PST 24
Peak memory 241152 kb
Host smart-b82ffa7c-b86c-49cd-ac2f-b97237e7c351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550340915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.2550340915 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_burst_write/latest


Test location /workspace/coverage/default/16.kmac_edn_timeout_error.2061550766
Short name T724
Test name
Test status
Simulation time 154055648 ps
CPU time 1.03 seconds
Started Feb 25 01:57:06 PM PST 24
Finished Feb 25 01:57:08 PM PST 24
Peak memory 218004 kb
Host smart-2f13f117-d2b0-46a0-bcc2-e25302943151
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2061550766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.2061550766 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/16.kmac_entropy_mode_error.1193496030
Short name T937
Test name
Test status
Simulation time 1278028506 ps
CPU time 26.92 seconds
Started Feb 25 01:57:07 PM PST 24
Finished Feb 25 01:57:34 PM PST 24
Peak memory 237556 kb
Host smart-57b2ef12-3d1d-4eaa-8dd2-10c574de5006
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1193496030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.1193496030 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/16.kmac_entropy_refresh.2123703516
Short name T49
Test name
Test status
Simulation time 6241660591 ps
CPU time 113.79 seconds
Started Feb 25 01:57:04 PM PST 24
Finished Feb 25 01:58:58 PM PST 24
Peak memory 235132 kb
Host smart-c52c6ff8-d6bd-4a17-b6a6-f7c821f7ff31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123703516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.2123703516 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/16.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/16.kmac_error.1611480813
Short name T492
Test name
Test status
Simulation time 4165357855 ps
CPU time 45.21 seconds
Started Feb 25 01:57:07 PM PST 24
Finished Feb 25 01:57:52 PM PST 24
Peak memory 243032 kb
Host smart-184d8e32-ad2a-4fb8-bbc6-dd5bd0169ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611480813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.1611480813 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_error/latest


Test location /workspace/coverage/default/16.kmac_key_error.4197035332
Short name T103
Test name
Test status
Simulation time 696783650 ps
CPU time 1.29 seconds
Started Feb 25 01:57:08 PM PST 24
Finished Feb 25 01:57:09 PM PST 24
Peak memory 218244 kb
Host smart-7f718bbc-354a-49a4-be27-4760febda67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197035332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.4197035332 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_key_error/latest


Test location /workspace/coverage/default/16.kmac_lc_escalation.311050908
Short name T717
Test name
Test status
Simulation time 58932536 ps
CPU time 1.25 seconds
Started Feb 25 01:57:07 PM PST 24
Finished Feb 25 01:57:08 PM PST 24
Peak memory 218368 kb
Host smart-0c3b3fa9-6dbc-4fc3-8f9b-09ca2a4dd086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311050908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.311050908 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/16.kmac_lc_escalation/latest


Test location /workspace/coverage/default/16.kmac_long_msg_and_output.1868976880
Short name T139
Test name
Test status
Simulation time 39600313500 ps
CPU time 2160.35 seconds
Started Feb 25 01:57:07 PM PST 24
Finished Feb 25 02:33:08 PM PST 24
Peak memory 407864 kb
Host smart-5da8ae0e-a5d3-4417-a26e-908ac1875944
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868976880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_a
nd_output.1868976880 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/16.kmac_sideload.2034912940
Short name T649
Test name
Test status
Simulation time 10181200539 ps
CPU time 411.85 seconds
Started Feb 25 01:57:05 PM PST 24
Finished Feb 25 02:03:58 PM PST 24
Peak memory 249424 kb
Host smart-0ae69735-7639-42ff-98e4-c8a5f6b97b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034912940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.2034912940 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_sideload/latest


Test location /workspace/coverage/default/16.kmac_smoke.1925300367
Short name T452
Test name
Test status
Simulation time 1027256307 ps
CPU time 43 seconds
Started Feb 25 01:56:49 PM PST 24
Finished Feb 25 01:57:32 PM PST 24
Peak memory 226592 kb
Host smart-6988e8b3-13a1-4e68-bb5e-432e6d983798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925300367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.1925300367 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_smoke/latest


Test location /workspace/coverage/default/16.kmac_stress_all.3146530289
Short name T28
Test name
Test status
Simulation time 17118053093 ps
CPU time 1051.23 seconds
Started Feb 25 01:57:05 PM PST 24
Finished Feb 25 02:14:37 PM PST 24
Peak memory 341260 kb
Host smart-4a4230dc-6bea-4470-8560-b7a0d59b020f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3146530289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.3146530289 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_stress_all/latest


Test location /workspace/coverage/default/16.kmac_test_vectors_kmac.1093807882
Short name T656
Test name
Test status
Simulation time 967297213 ps
CPU time 6.97 seconds
Started Feb 25 01:57:06 PM PST 24
Finished Feb 25 01:57:14 PM PST 24
Peak memory 219868 kb
Host smart-20262b9a-b2ce-4d77-af21-9ea6007f9158
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093807882 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.kmac_test_vectors_kmac.1093807882 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/16.kmac_test_vectors_kmac_xof.3695044731
Short name T283
Test name
Test status
Simulation time 402226671 ps
CPU time 6.42 seconds
Started Feb 25 01:57:08 PM PST 24
Finished Feb 25 01:57:15 PM PST 24
Peak memory 218380 kb
Host smart-37fa180f-c572-4d43-83a5-ac2ae176db49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695044731 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.kmac_test_vectors_kmac_xof.3695044731 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_224.89607162
Short name T336
Test name
Test status
Simulation time 21351404366 ps
CPU time 2292.64 seconds
Started Feb 25 01:57:05 PM PST 24
Finished Feb 25 02:35:19 PM PST 24
Peak memory 401836 kb
Host smart-1be66ef8-66c2-4974-833d-4ff0976b848f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=89607162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_224.89607162 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_256.1271566226
Short name T230
Test name
Test status
Simulation time 83392136615 ps
CPU time 2161.9 seconds
Started Feb 25 01:57:06 PM PST 24
Finished Feb 25 02:33:08 PM PST 24
Peak memory 396280 kb
Host smart-f5d0a2b1-35d3-4fab-9585-4df72cec7dd8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1271566226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_256.1271566226 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_384.1076583439
Short name T633
Test name
Test status
Simulation time 62924819461 ps
CPU time 1758.22 seconds
Started Feb 25 01:57:05 PM PST 24
Finished Feb 25 02:26:24 PM PST 24
Peak memory 345624 kb
Host smart-038a7962-2241-4c80-b933-58e39a6fcc7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1076583439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_384.1076583439 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_512.1358430528
Short name T854
Test name
Test status
Simulation time 34866861343 ps
CPU time 1357.43 seconds
Started Feb 25 01:57:08 PM PST 24
Finished Feb 25 02:19:46 PM PST 24
Peak memory 303800 kb
Host smart-1af9e832-742e-409c-b4c9-c92a032f666f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1358430528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_512.1358430528 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/16.kmac_test_vectors_shake_128.352805823
Short name T929
Test name
Test status
Simulation time 94294687461 ps
CPU time 5120.97 seconds
Started Feb 25 01:57:08 PM PST 24
Finished Feb 25 03:22:29 PM PST 24
Peak memory 645104 kb
Host smart-3034a217-a2b3-4a69-8f95-ad2719af62c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=352805823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_128.352805823 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/16.kmac_test_vectors_shake_256.1419038217
Short name T490
Test name
Test status
Simulation time 104790726052 ps
CPU time 4491.96 seconds
Started Feb 25 01:57:06 PM PST 24
Finished Feb 25 03:11:59 PM PST 24
Peak memory 573756 kb
Host smart-4a438a66-078d-402b-9b0b-2b777997cc4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1419038217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_256.1419038217 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/17.kmac_alert_test.2304431555
Short name T910
Test name
Test status
Simulation time 58604495 ps
CPU time 0.85 seconds
Started Feb 25 01:57:12 PM PST 24
Finished Feb 25 01:57:13 PM PST 24
Peak memory 219092 kb
Host smart-598c625c-b8ef-463e-92e1-06a9d235934e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304431555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.2304431555 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_alert_test/latest


Test location /workspace/coverage/default/17.kmac_app.1342471462
Short name T99
Test name
Test status
Simulation time 678235986 ps
CPU time 35.52 seconds
Started Feb 25 01:57:11 PM PST 24
Finished Feb 25 01:57:47 PM PST 24
Peak memory 234668 kb
Host smart-a391ce3e-f6c7-4bca-8ff0-58862aa0b6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342471462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.1342471462 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_app/latest


Test location /workspace/coverage/default/17.kmac_burst_write.2621117240
Short name T776
Test name
Test status
Simulation time 124629604977 ps
CPU time 1301.8 seconds
Started Feb 25 01:57:04 PM PST 24
Finished Feb 25 02:18:47 PM PST 24
Peak memory 239492 kb
Host smart-8e93e675-8926-4c8a-8dfc-88665d8dafd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621117240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.2621117240 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_burst_write/latest


Test location /workspace/coverage/default/17.kmac_edn_timeout_error.215871014
Short name T983
Test name
Test status
Simulation time 1362582364 ps
CPU time 38.39 seconds
Started Feb 25 01:57:15 PM PST 24
Finished Feb 25 01:57:54 PM PST 24
Peak memory 242796 kb
Host smart-f249a92b-17f5-410a-ab61-c18f2a51d2f5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=215871014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.215871014 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/17.kmac_entropy_mode_error.477983327
Short name T881
Test name
Test status
Simulation time 163755976 ps
CPU time 1.24 seconds
Started Feb 25 01:57:17 PM PST 24
Finished Feb 25 01:57:19 PM PST 24
Peak memory 218228 kb
Host smart-887929a1-bd4e-4cad-a142-553abca6f5c7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=477983327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.477983327 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/17.kmac_entropy_refresh.1238106997
Short name T710
Test name
Test status
Simulation time 16717525991 ps
CPU time 424.87 seconds
Started Feb 25 01:57:12 PM PST 24
Finished Feb 25 02:04:17 PM PST 24
Peak memory 255904 kb
Host smart-a7ec1be0-be0d-4414-975f-ce64f6b64785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238106997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.1238106997 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/17.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/17.kmac_error.1130412421
Short name T411
Test name
Test status
Simulation time 17212343055 ps
CPU time 87.81 seconds
Started Feb 25 01:57:16 PM PST 24
Finished Feb 25 01:58:44 PM PST 24
Peak memory 240524 kb
Host smart-56043b15-2cce-4322-a27b-65f9ec0bea39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130412421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.1130412421 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_error/latest


Test location /workspace/coverage/default/17.kmac_key_error.933864333
Short name T136
Test name
Test status
Simulation time 1871984999 ps
CPU time 2.94 seconds
Started Feb 25 01:57:14 PM PST 24
Finished Feb 25 01:57:17 PM PST 24
Peak memory 218300 kb
Host smart-edde5c4a-2f68-4b0f-bc53-da6bb1895ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933864333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.933864333 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_key_error/latest


Test location /workspace/coverage/default/17.kmac_lc_escalation.2786404152
Short name T1055
Test name
Test status
Simulation time 47789816 ps
CPU time 1.44 seconds
Started Feb 25 01:57:16 PM PST 24
Finished Feb 25 01:57:17 PM PST 24
Peak memory 218316 kb
Host smart-3f5c74a5-b7b6-41a3-94bb-1fb09fdc270c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786404152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.2786404152 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/17.kmac_lc_escalation/latest


Test location /workspace/coverage/default/17.kmac_long_msg_and_output.3256031173
Short name T311
Test name
Test status
Simulation time 8406935925 ps
CPU time 1086.25 seconds
Started Feb 25 01:57:04 PM PST 24
Finished Feb 25 02:15:11 PM PST 24
Peak memory 297868 kb
Host smart-590c32cc-8ca3-442b-aead-accc89a53fd8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256031173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_a
nd_output.3256031173 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/17.kmac_sideload.2885596549
Short name T334
Test name
Test status
Simulation time 8392442458 ps
CPU time 263.81 seconds
Started Feb 25 01:57:06 PM PST 24
Finished Feb 25 02:01:30 PM PST 24
Peak memory 244380 kb
Host smart-cb650061-56c6-410f-9215-4602d1278814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885596549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.2885596549 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_sideload/latest


Test location /workspace/coverage/default/17.kmac_smoke.2321117972
Short name T848
Test name
Test status
Simulation time 17671946689 ps
CPU time 99.4 seconds
Started Feb 25 01:57:05 PM PST 24
Finished Feb 25 01:58:45 PM PST 24
Peak memory 226612 kb
Host smart-d9f1dbdb-fc4f-46db-a157-c81615704242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321117972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.2321117972 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_smoke/latest


Test location /workspace/coverage/default/17.kmac_stress_all.3328373673
Short name T1058
Test name
Test status
Simulation time 83395523394 ps
CPU time 1246.29 seconds
Started Feb 25 01:57:18 PM PST 24
Finished Feb 25 02:18:04 PM PST 24
Peak memory 334528 kb
Host smart-961afe1f-2bd5-40ce-b04b-9bfc14023d3d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3328373673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.3328373673 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_stress_all/latest


Test location /workspace/coverage/default/17.kmac_test_vectors_kmac.4056939332
Short name T337
Test name
Test status
Simulation time 571695551 ps
CPU time 6.5 seconds
Started Feb 25 01:57:17 PM PST 24
Finished Feb 25 01:57:23 PM PST 24
Peak memory 218472 kb
Host smart-22abb73f-1bb4-43fc-aa2f-c51306c19ed2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056939332 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.kmac_test_vectors_kmac.4056939332 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/17.kmac_test_vectors_kmac_xof.3383128661
Short name T667
Test name
Test status
Simulation time 98409941 ps
CPU time 5.95 seconds
Started Feb 25 01:57:17 PM PST 24
Finished Feb 25 01:57:23 PM PST 24
Peak memory 218384 kb
Host smart-5b4790b5-e9df-4ee5-815c-5912f730851c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383128661 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.kmac_test_vectors_kmac_xof.3383128661 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_224.3616594940
Short name T345
Test name
Test status
Simulation time 73386973090 ps
CPU time 2210.98 seconds
Started Feb 25 01:57:07 PM PST 24
Finished Feb 25 02:33:58 PM PST 24
Peak memory 404528 kb
Host smart-ad56b0e0-d17b-4880-a01f-1eb1484ebce5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3616594940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_224.3616594940 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_256.771552988
Short name T758
Test name
Test status
Simulation time 1325336481311 ps
CPU time 2860.46 seconds
Started Feb 25 01:57:07 PM PST 24
Finished Feb 25 02:44:47 PM PST 24
Peak memory 392868 kb
Host smart-9b25b269-eb46-4626-8a6d-c5d1e8a93e63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=771552988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_256.771552988 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_384.2234476298
Short name T685
Test name
Test status
Simulation time 29116598701 ps
CPU time 1635.86 seconds
Started Feb 25 01:57:05 PM PST 24
Finished Feb 25 02:24:22 PM PST 24
Peak memory 338932 kb
Host smart-460049df-b1f0-4b97-999d-48cf568782d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2234476298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_384.2234476298 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_512.2190179173
Short name T525
Test name
Test status
Simulation time 168701868279 ps
CPU time 1349.78 seconds
Started Feb 25 01:57:07 PM PST 24
Finished Feb 25 02:19:37 PM PST 24
Peak memory 305728 kb
Host smart-01a4557e-4114-405c-ad49-40a8c4db39f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2190179173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_512.2190179173 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/17.kmac_test_vectors_shake_128.865670612
Short name T196
Test name
Test status
Simulation time 261847586820 ps
CPU time 5526.42 seconds
Started Feb 25 01:57:17 PM PST 24
Finished Feb 25 03:29:24 PM PST 24
Peak memory 658396 kb
Host smart-a297a154-b4a7-45da-a599-132ab70e47b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=865670612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_128.865670612 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/17.kmac_test_vectors_shake_256.111110700
Short name T1001
Test name
Test status
Simulation time 1841974308675 ps
CPU time 6214.44 seconds
Started Feb 25 01:57:18 PM PST 24
Finished Feb 25 03:40:53 PM PST 24
Peak memory 581080 kb
Host smart-1681c154-df95-4d5b-94df-678238de6d9c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=111110700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_256.111110700 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/18.kmac_alert_test.3042213928
Short name T575
Test name
Test status
Simulation time 15864063 ps
CPU time 0.87 seconds
Started Feb 25 01:57:31 PM PST 24
Finished Feb 25 01:57:32 PM PST 24
Peak memory 219316 kb
Host smart-31462be1-3900-4c4b-912c-2438dc2c2db6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042213928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.3042213928 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_alert_test/latest


Test location /workspace/coverage/default/18.kmac_app.1971734336
Short name T934
Test name
Test status
Simulation time 34115895758 ps
CPU time 343.72 seconds
Started Feb 25 01:57:30 PM PST 24
Finished Feb 25 02:03:14 PM PST 24
Peak memory 252496 kb
Host smart-a2fa64cc-0ead-4226-8bca-aadfac33093f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971734336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.1971734336 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_app/latest


Test location /workspace/coverage/default/18.kmac_burst_write.441410649
Short name T148
Test name
Test status
Simulation time 5520108020 ps
CPU time 686.57 seconds
Started Feb 25 01:57:14 PM PST 24
Finished Feb 25 02:08:41 PM PST 24
Peak memory 240080 kb
Host smart-ca814051-9fea-42e2-a30e-db9cf21a1622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441410649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.441410649 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_burst_write/latest


Test location /workspace/coverage/default/18.kmac_edn_timeout_error.362752109
Short name T71
Test name
Test status
Simulation time 181852113 ps
CPU time 1.35 seconds
Started Feb 25 01:57:29 PM PST 24
Finished Feb 25 01:57:30 PM PST 24
Peak memory 218360 kb
Host smart-9145898b-9078-46b6-a954-fd22a17e088a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=362752109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.362752109 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/18.kmac_entropy_mode_error.567056175
Short name T1027
Test name
Test status
Simulation time 32750190 ps
CPU time 1.12 seconds
Started Feb 25 01:57:28 PM PST 24
Finished Feb 25 01:57:30 PM PST 24
Peak memory 218308 kb
Host smart-54f4ac0e-a272-4d56-91f7-bd469b8cda9d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=567056175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.567056175 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/18.kmac_entropy_refresh.1981377819
Short name T29
Test name
Test status
Simulation time 18223356059 ps
CPU time 409.39 seconds
Started Feb 25 01:57:29 PM PST 24
Finished Feb 25 02:04:18 PM PST 24
Peak memory 251272 kb
Host smart-5c2e7e52-2014-485f-b835-236f080d7f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981377819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.1981377819 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/18.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/18.kmac_error.1284395932
Short name T669
Test name
Test status
Simulation time 58674956590 ps
CPU time 521.04 seconds
Started Feb 25 01:57:30 PM PST 24
Finished Feb 25 02:06:11 PM PST 24
Peak memory 268708 kb
Host smart-2ba27d4a-44c3-4ba3-b7dc-44d95bed2bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284395932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.1284395932 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_error/latest


Test location /workspace/coverage/default/18.kmac_key_error.1384117256
Short name T911
Test name
Test status
Simulation time 71379940 ps
CPU time 1.07 seconds
Started Feb 25 01:57:28 PM PST 24
Finished Feb 25 01:57:30 PM PST 24
Peak memory 218184 kb
Host smart-c7de7a82-2b34-42e9-9ac5-3370876d7972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384117256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.1384117256 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_key_error/latest


Test location /workspace/coverage/default/18.kmac_long_msg_and_output.3398307579
Short name T228
Test name
Test status
Simulation time 4947995058 ps
CPU time 308.21 seconds
Started Feb 25 01:57:10 PM PST 24
Finished Feb 25 02:02:18 PM PST 24
Peak memory 244616 kb
Host smart-691a88b8-813d-4f1e-a7a9-98263c4c048f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398307579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_a
nd_output.3398307579 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/18.kmac_sideload.3300236822
Short name T1033
Test name
Test status
Simulation time 11502209639 ps
CPU time 279.73 seconds
Started Feb 25 01:57:16 PM PST 24
Finished Feb 25 02:01:56 PM PST 24
Peak memory 244300 kb
Host smart-19d4cdc9-d326-4935-9aff-011b7520e978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300236822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.3300236822 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_sideload/latest


Test location /workspace/coverage/default/18.kmac_smoke.1050285996
Short name T381
Test name
Test status
Simulation time 10420449624 ps
CPU time 73.69 seconds
Started Feb 25 01:57:15 PM PST 24
Finished Feb 25 01:58:29 PM PST 24
Peak memory 226560 kb
Host smart-cbf5349d-2956-478c-a21e-bdea9d383b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050285996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.1050285996 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_smoke/latest


Test location /workspace/coverage/default/18.kmac_stress_all.1387769021
Short name T907
Test name
Test status
Simulation time 7369882349 ps
CPU time 36.03 seconds
Started Feb 25 01:57:24 PM PST 24
Finished Feb 25 01:58:00 PM PST 24
Peak memory 236164 kb
Host smart-769ddbf7-8605-49db-ae06-5f29bc0c1ea9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1387769021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.1387769021 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_stress_all/latest


Test location /workspace/coverage/default/18.kmac_test_vectors_kmac.2997343584
Short name T440
Test name
Test status
Simulation time 537890972 ps
CPU time 6.14 seconds
Started Feb 25 01:57:17 PM PST 24
Finished Feb 25 01:57:23 PM PST 24
Peak memory 218408 kb
Host smart-73d5e414-772d-423c-8ea3-382f61e78ecc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997343584 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.kmac_test_vectors_kmac.2997343584 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/18.kmac_test_vectors_kmac_xof.926794078
Short name T1056
Test name
Test status
Simulation time 564427518 ps
CPU time 6.47 seconds
Started Feb 25 01:57:11 PM PST 24
Finished Feb 25 01:57:18 PM PST 24
Peak memory 219836 kb
Host smart-98a70771-cead-496d-80f0-3c9e6f8a7c4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926794078 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.kmac_test_vectors_kmac_xof.926794078 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_224.3915295603
Short name T895
Test name
Test status
Simulation time 97025453447 ps
CPU time 2492.59 seconds
Started Feb 25 01:57:14 PM PST 24
Finished Feb 25 02:38:47 PM PST 24
Peak memory 394312 kb
Host smart-90d0b04c-a082-455a-b145-29fb48917e59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3915295603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_224.3915295603 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_256.1408816688
Short name T280
Test name
Test status
Simulation time 38557459946 ps
CPU time 2071.57 seconds
Started Feb 25 01:57:10 PM PST 24
Finished Feb 25 02:31:42 PM PST 24
Peak memory 382908 kb
Host smart-7157949e-4dca-4bf4-b5f5-010eb1c92ea5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1408816688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_256.1408816688 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_384.1640090902
Short name T201
Test name
Test status
Simulation time 203096376045 ps
CPU time 1941.15 seconds
Started Feb 25 01:57:16 PM PST 24
Finished Feb 25 02:29:38 PM PST 24
Peak memory 348840 kb
Host smart-9815ed1a-3937-4c67-b567-c192ca4f380a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1640090902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_384.1640090902 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_512.3223963074
Short name T722
Test name
Test status
Simulation time 50989742187 ps
CPU time 1525.32 seconds
Started Feb 25 01:57:10 PM PST 24
Finished Feb 25 02:22:36 PM PST 24
Peak memory 305436 kb
Host smart-10080892-2674-41f0-b3c0-1dcef3f009d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3223963074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_512.3223963074 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/18.kmac_test_vectors_shake_128.4026531009
Short name T349
Test name
Test status
Simulation time 60353163154 ps
CPU time 5434.45 seconds
Started Feb 25 01:57:12 PM PST 24
Finished Feb 25 03:27:47 PM PST 24
Peak memory 660316 kb
Host smart-e74dd5b4-37c7-4d5a-8e4f-e2ea353189ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4026531009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_128.4026531009 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/18.kmac_test_vectors_shake_256.319154538
Short name T347
Test name
Test status
Simulation time 802343537124 ps
CPU time 5472.28 seconds
Started Feb 25 01:57:17 PM PST 24
Finished Feb 25 03:28:30 PM PST 24
Peak memory 574064 kb
Host smart-ecb54fa3-03a3-449d-be3a-3c1679f9311f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=319154538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_256.319154538 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/19.kmac_alert_test.2559606463
Short name T991
Test name
Test status
Simulation time 48660007 ps
CPU time 0.85 seconds
Started Feb 25 01:57:30 PM PST 24
Finished Feb 25 01:57:31 PM PST 24
Peak memory 219324 kb
Host smart-d49eae82-6a74-4dc0-806a-ea253e9a83de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559606463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.2559606463 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_alert_test/latest


Test location /workspace/coverage/default/19.kmac_burst_write.4040924626
Short name T385
Test name
Test status
Simulation time 2762081689 ps
CPU time 330.17 seconds
Started Feb 25 01:57:29 PM PST 24
Finished Feb 25 02:02:59 PM PST 24
Peak memory 231008 kb
Host smart-4ad13ad4-3292-4720-ad78-f681dcda6d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040924626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.4040924626 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_burst_write/latest


Test location /workspace/coverage/default/19.kmac_edn_timeout_error.146611876
Short name T819
Test name
Test status
Simulation time 4266560917 ps
CPU time 38.75 seconds
Started Feb 25 01:57:33 PM PST 24
Finished Feb 25 01:58:12 PM PST 24
Peak memory 235880 kb
Host smart-2e80bdf1-1c6f-4e33-bcb9-a4256654750e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=146611876 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.146611876 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/19.kmac_entropy_mode_error.3646340888
Short name T207
Test name
Test status
Simulation time 1587358712 ps
CPU time 15.34 seconds
Started Feb 25 01:57:29 PM PST 24
Finished Feb 25 01:57:44 PM PST 24
Peak memory 234904 kb
Host smart-099070f8-6898-4414-83a5-8e2996442b69
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3646340888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.3646340888 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/19.kmac_entropy_refresh.1742774606
Short name T1061
Test name
Test status
Simulation time 22128177793 ps
CPU time 358.6 seconds
Started Feb 25 01:57:34 PM PST 24
Finished Feb 25 02:03:33 PM PST 24
Peak memory 253184 kb
Host smart-3fdfbd05-1eff-4b24-8b71-fac199d33424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742774606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.1742774606 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/19.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/19.kmac_error.1109675713
Short name T768
Test name
Test status
Simulation time 18058397325 ps
CPU time 166.2 seconds
Started Feb 25 01:57:31 PM PST 24
Finished Feb 25 02:00:17 PM PST 24
Peak memory 251224 kb
Host smart-df832d2b-8af2-41ca-8811-f746e50e3592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109675713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.1109675713 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_error/latest


Test location /workspace/coverage/default/19.kmac_key_error.2585618042
Short name T603
Test name
Test status
Simulation time 1258734172 ps
CPU time 7.58 seconds
Started Feb 25 01:57:35 PM PST 24
Finished Feb 25 01:57:42 PM PST 24
Peak memory 218368 kb
Host smart-a6bcc5e0-6bf0-4d03-9cee-b2eacc73ed0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585618042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.2585618042 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_key_error/latest


Test location /workspace/coverage/default/19.kmac_lc_escalation.2403957465
Short name T432
Test name
Test status
Simulation time 64430462 ps
CPU time 1.4 seconds
Started Feb 25 01:57:29 PM PST 24
Finished Feb 25 01:57:31 PM PST 24
Peak memory 219284 kb
Host smart-025443d8-9026-47af-82b2-f527ebf77965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403957465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.2403957465 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/19.kmac_lc_escalation/latest


Test location /workspace/coverage/default/19.kmac_long_msg_and_output.1515052711
Short name T1051
Test name
Test status
Simulation time 337709938983 ps
CPU time 2307.8 seconds
Started Feb 25 01:57:27 PM PST 24
Finished Feb 25 02:35:55 PM PST 24
Peak memory 397396 kb
Host smart-c18babef-f6a6-4994-aed8-4174bd837586
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515052711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_a
nd_output.1515052711 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/19.kmac_sideload.3465623228
Short name T1064
Test name
Test status
Simulation time 15101884722 ps
CPU time 530.08 seconds
Started Feb 25 01:57:27 PM PST 24
Finished Feb 25 02:06:17 PM PST 24
Peak memory 256676 kb
Host smart-7b80d0ab-2178-4f76-a6e3-14f67b416770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465623228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.3465623228 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_sideload/latest


Test location /workspace/coverage/default/19.kmac_smoke.1461364840
Short name T233
Test name
Test status
Simulation time 14486733408 ps
CPU time 38.64 seconds
Started Feb 25 01:57:30 PM PST 24
Finished Feb 25 01:58:09 PM PST 24
Peak memory 226660 kb
Host smart-7e548b11-dad0-40bf-83fe-d24c2867d914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461364840 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.1461364840 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_smoke/latest


Test location /workspace/coverage/default/19.kmac_stress_all.101552552
Short name T699
Test name
Test status
Simulation time 13036555676 ps
CPU time 219.74 seconds
Started Feb 25 01:57:32 PM PST 24
Finished Feb 25 02:01:12 PM PST 24
Peak memory 285112 kb
Host smart-bcb25ce6-2ef6-4a33-9a83-339c9d20004a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=101552552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.101552552 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_stress_all/latest


Test location /workspace/coverage/default/19.kmac_stress_all_with_rand_reset.3329413389
Short name T124
Test name
Test status
Simulation time 71814593848 ps
CPU time 446.52 seconds
Started Feb 25 01:57:33 PM PST 24
Finished Feb 25 02:04:59 PM PST 24
Peak memory 284340 kb
Host smart-d2527e60-0145-4fb9-ace6-179c75b59136
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3329413389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all_with_rand_reset.3329413389 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/19.kmac_test_vectors_kmac.1563335239
Short name T330
Test name
Test status
Simulation time 851755444 ps
CPU time 6.37 seconds
Started Feb 25 01:57:26 PM PST 24
Finished Feb 25 01:57:33 PM PST 24
Peak memory 219876 kb
Host smart-b2a5f9e1-e762-4614-a69b-edf88ea930e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563335239 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.kmac_test_vectors_kmac.1563335239 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/19.kmac_test_vectors_kmac_xof.1233414285
Short name T558
Test name
Test status
Simulation time 967058187 ps
CPU time 6.66 seconds
Started Feb 25 01:57:34 PM PST 24
Finished Feb 25 01:57:40 PM PST 24
Peak memory 218416 kb
Host smart-4c3d4733-4bc4-406d-aec5-967bb6262af2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233414285 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.kmac_test_vectors_kmac_xof.1233414285 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_224.2648177149
Short name T208
Test name
Test status
Simulation time 136716986711 ps
CPU time 2247.83 seconds
Started Feb 25 01:57:23 PM PST 24
Finished Feb 25 02:34:52 PM PST 24
Peak memory 402988 kb
Host smart-eece5860-ee88-413d-b86a-014c8a3f909b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2648177149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_224.2648177149 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_256.1386439086
Short name T810
Test name
Test status
Simulation time 164154837350 ps
CPU time 2135.5 seconds
Started Feb 25 01:57:30 PM PST 24
Finished Feb 25 02:33:06 PM PST 24
Peak memory 391424 kb
Host smart-63c6b1b5-7000-4b37-85fc-b6e2be2250c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1386439086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_256.1386439086 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_384.2229224255
Short name T375
Test name
Test status
Simulation time 394151490742 ps
CPU time 1879.79 seconds
Started Feb 25 01:57:26 PM PST 24
Finished Feb 25 02:28:47 PM PST 24
Peak memory 339504 kb
Host smart-6997deb6-2c4f-4eeb-b704-7d7e7fbbd6dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2229224255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_384.2229224255 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_512.1472383711
Short name T618
Test name
Test status
Simulation time 49400600268 ps
CPU time 1311.18 seconds
Started Feb 25 01:57:23 PM PST 24
Finished Feb 25 02:19:14 PM PST 24
Peak memory 296224 kb
Host smart-cf8228c3-da90-4da1-ad09-ab44b18dd517
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1472383711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_512.1472383711 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/19.kmac_test_vectors_shake_128.1573987562
Short name T838
Test name
Test status
Simulation time 259039250044 ps
CPU time 5508.67 seconds
Started Feb 25 01:57:29 PM PST 24
Finished Feb 25 03:29:19 PM PST 24
Peak memory 642148 kb
Host smart-1bbf0360-9111-4e69-93cc-e2e3209de69a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1573987562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_128.1573987562 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/19.kmac_test_vectors_shake_256.664094989
Short name T164
Test name
Test status
Simulation time 680947549176 ps
CPU time 5067.64 seconds
Started Feb 25 01:57:28 PM PST 24
Finished Feb 25 03:21:56 PM PST 24
Peak memory 569568 kb
Host smart-d3f86ec5-ce01-4733-a7c6-fa05e6dd5d1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=664094989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_256.664094989 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/2.kmac_alert_test.2093918457
Short name T454
Test name
Test status
Simulation time 30910636 ps
CPU time 0.87 seconds
Started Feb 25 01:55:30 PM PST 24
Finished Feb 25 01:55:31 PM PST 24
Peak memory 218100 kb
Host smart-f194b2e1-b15d-43da-8929-700de493d1aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093918457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.2093918457 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_alert_test/latest


Test location /workspace/coverage/default/2.kmac_app.649903704
Short name T172
Test name
Test status
Simulation time 19368431947 ps
CPU time 263.37 seconds
Started Feb 25 01:55:29 PM PST 24
Finished Feb 25 01:59:53 PM PST 24
Peak memory 248592 kb
Host smart-769377f7-4def-42c5-8a0e-406e6a3a6adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649903704 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.649903704 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_app/latest


Test location /workspace/coverage/default/2.kmac_app_with_partial_data.3446026897
Short name T805
Test name
Test status
Simulation time 8732282469 ps
CPU time 336.32 seconds
Started Feb 25 01:55:30 PM PST 24
Finished Feb 25 02:01:07 PM PST 24
Peak memory 252156 kb
Host smart-c114d3e6-0ac0-4155-b034-255ba12f34ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446026897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.3446026897 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_app_with_partial_data/latest


Test location /workspace/coverage/default/2.kmac_burst_write.2973698968
Short name T1023
Test name
Test status
Simulation time 46230568664 ps
CPU time 1129.16 seconds
Started Feb 25 01:55:30 PM PST 24
Finished Feb 25 02:14:19 PM PST 24
Peak memory 242856 kb
Host smart-bba0e1ad-f797-4bea-b6ff-b93ed6a5957f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973698968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.2973698968 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_burst_write/latest


Test location /workspace/coverage/default/2.kmac_edn_timeout_error.3736758027
Short name T775
Test name
Test status
Simulation time 8164097856 ps
CPU time 26.7 seconds
Started Feb 25 01:55:29 PM PST 24
Finished Feb 25 01:55:56 PM PST 24
Peak memory 228200 kb
Host smart-1aec4cdf-e13d-4a96-9ae7-31cf84ef7438
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3736758027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.3736758027 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/2.kmac_entropy_mode_error.4045081415
Short name T648
Test name
Test status
Simulation time 146687206 ps
CPU time 1.27 seconds
Started Feb 25 01:55:35 PM PST 24
Finished Feb 25 01:55:37 PM PST 24
Peak memory 218296 kb
Host smart-227c297b-6eb7-4dae-8d3a-8b576f4a76d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4045081415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.4045081415 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/2.kmac_entropy_ready_error.237368542
Short name T962
Test name
Test status
Simulation time 27194627373 ps
CPU time 72.01 seconds
Started Feb 25 01:55:31 PM PST 24
Finished Feb 25 01:56:43 PM PST 24
Peak memory 221616 kb
Host smart-d25a95bc-b955-4a3f-b57d-deac00aea317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237368542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.237368542 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_ready_error/latest


Test location /workspace/coverage/default/2.kmac_entropy_refresh.483938084
Short name T732
Test name
Test status
Simulation time 14416304965 ps
CPU time 46.8 seconds
Started Feb 25 01:55:30 PM PST 24
Finished Feb 25 01:56:17 PM PST 24
Peak memory 236620 kb
Host smart-7e51a8da-6b4d-4e31-bfb8-057f5f790b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483938084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.483938084 +enable_masking=1 +sw_
key_masked=0
Directory /workspace/2.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/2.kmac_error.2280745877
Short name T421
Test name
Test status
Simulation time 944062718 ps
CPU time 32.26 seconds
Started Feb 25 01:55:32 PM PST 24
Finished Feb 25 01:56:04 PM PST 24
Peak memory 235432 kb
Host smart-25a24df5-2455-4703-b6a4-827046105b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280745877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.2280745877 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_error/latest


Test location /workspace/coverage/default/2.kmac_key_error.1157749000
Short name T584
Test name
Test status
Simulation time 968462126 ps
CPU time 6.05 seconds
Started Feb 25 01:55:29 PM PST 24
Finished Feb 25 01:55:36 PM PST 24
Peak memory 218316 kb
Host smart-1b0f9dfb-0457-4331-b060-d1b80a287f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157749000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.1157749000 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_key_error/latest


Test location /workspace/coverage/default/2.kmac_lc_escalation.3228898702
Short name T26
Test name
Test status
Simulation time 158715361 ps
CPU time 1.53 seconds
Started Feb 25 01:55:30 PM PST 24
Finished Feb 25 01:55:31 PM PST 24
Peak memory 219288 kb
Host smart-6f6f2669-b04a-44bd-b22c-c44fe11a888e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228898702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.3228898702 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/2.kmac_lc_escalation/latest


Test location /workspace/coverage/default/2.kmac_long_msg_and_output.2215968836
Short name T320
Test name
Test status
Simulation time 262916117020 ps
CPU time 1765.73 seconds
Started Feb 25 01:55:18 PM PST 24
Finished Feb 25 02:24:45 PM PST 24
Peak memory 354548 kb
Host smart-50acdfd3-fa34-464f-a195-d9f780f7ace7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215968836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_an
d_output.2215968836 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/2.kmac_mubi.1708771862
Short name T880
Test name
Test status
Simulation time 8922638760 ps
CPU time 289.24 seconds
Started Feb 25 01:55:34 PM PST 24
Finished Feb 25 02:00:24 PM PST 24
Peak memory 245932 kb
Host smart-a9009e39-6f24-423e-a9fe-3fddd507324d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708771862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.1708771862 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mubi/latest


Test location /workspace/coverage/default/2.kmac_sec_cm.1669843344
Short name T8
Test name
Test status
Simulation time 2507819359 ps
CPU time 47.92 seconds
Started Feb 25 01:55:32 PM PST 24
Finished Feb 25 01:56:21 PM PST 24
Peak memory 256928 kb
Host smart-09ac1954-bec7-4352-8f4a-1cf81dba245f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669843344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.1669843344 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/2.kmac_sec_cm/latest


Test location /workspace/coverage/default/2.kmac_sideload.261518385
Short name T323
Test name
Test status
Simulation time 6315613903 ps
CPU time 55.29 seconds
Started Feb 25 01:55:27 PM PST 24
Finished Feb 25 01:56:23 PM PST 24
Peak memory 228644 kb
Host smart-798af815-1eb7-465c-b13b-d6ed8020eb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261518385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.261518385 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_sideload/latest


Test location /workspace/coverage/default/2.kmac_smoke.2374350846
Short name T300
Test name
Test status
Simulation time 1881072162 ps
CPU time 67.25 seconds
Started Feb 25 01:55:18 PM PST 24
Finished Feb 25 01:56:26 PM PST 24
Peak memory 226592 kb
Host smart-2cb67579-f957-463b-8fc8-42353b1820f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374350846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.2374350846 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_smoke/latest


Test location /workspace/coverage/default/2.kmac_stress_all.1308562324
Short name T737
Test name
Test status
Simulation time 564402558 ps
CPU time 6.68 seconds
Started Feb 25 01:55:30 PM PST 24
Finished Feb 25 01:55:36 PM PST 24
Peak memory 218336 kb
Host smart-6930d3d9-192e-479d-a856-118161bc6fbe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1308562324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.1308562324 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_stress_all/latest


Test location /workspace/coverage/default/2.kmac_test_vectors_kmac.806378461
Short name T733
Test name
Test status
Simulation time 198747359 ps
CPU time 6.3 seconds
Started Feb 25 01:55:33 PM PST 24
Finished Feb 25 01:55:41 PM PST 24
Peak memory 219824 kb
Host smart-9b43bf87-dfe6-4f1a-a163-a18769ad4fd5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806378461 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.kmac_test_vectors_kmac.806378461 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/2.kmac_test_vectors_kmac_xof.2130505359
Short name T365
Test name
Test status
Simulation time 196099730 ps
CPU time 5.66 seconds
Started Feb 25 01:55:28 PM PST 24
Finished Feb 25 01:55:34 PM PST 24
Peak memory 218248 kb
Host smart-cbaa58c6-f2fa-4162-89c6-ca640dcdd81b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130505359 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.kmac_test_vectors_kmac_xof.2130505359 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_224.2732716907
Short name T222
Test name
Test status
Simulation time 194157206006 ps
CPU time 2496 seconds
Started Feb 25 01:55:20 PM PST 24
Finished Feb 25 02:36:57 PM PST 24
Peak memory 391536 kb
Host smart-9f4f0b91-fe56-447b-a5ef-c1da8082d2f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2732716907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.2732716907 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_256.4042556326
Short name T875
Test name
Test status
Simulation time 1021513501907 ps
CPU time 2468.45 seconds
Started Feb 25 01:55:19 PM PST 24
Finished Feb 25 02:36:28 PM PST 24
Peak memory 389104 kb
Host smart-6a3b9e88-1166-4b25-beae-2651d64a5f75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4042556326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.4042556326 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_384.1481320170
Short name T576
Test name
Test status
Simulation time 616858082325 ps
CPU time 1711.58 seconds
Started Feb 25 01:55:31 PM PST 24
Finished Feb 25 02:24:03 PM PST 24
Peak memory 342724 kb
Host smart-9673fdf3-a9ff-4bdd-99cd-288457db9884
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1481320170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.1481320170 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_512.4101978568
Short name T133
Test name
Test status
Simulation time 10798019146 ps
CPU time 1141.01 seconds
Started Feb 25 01:55:29 PM PST 24
Finished Feb 25 02:14:30 PM PST 24
Peak memory 305508 kb
Host smart-d22776a8-18f9-49f1-ae44-8913a49237d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4101978568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.4101978568 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/2.kmac_test_vectors_shake_128.3593860619
Short name T998
Test name
Test status
Simulation time 176742449718 ps
CPU time 5910.22 seconds
Started Feb 25 01:55:29 PM PST 24
Finished Feb 25 03:34:00 PM PST 24
Peak memory 654332 kb
Host smart-4bde32c6-5549-435a-874c-3af13d9372ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3593860619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.3593860619 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/2.kmac_test_vectors_shake_256.913639242
Short name T281
Test name
Test status
Simulation time 304923517529 ps
CPU time 4986.88 seconds
Started Feb 25 01:55:32 PM PST 24
Finished Feb 25 03:18:40 PM PST 24
Peak memory 572976 kb
Host smart-f5edf044-6e61-41b7-a4cf-55bce732bbd1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=913639242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.913639242 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/20.kmac_alert_test.4087531545
Short name T216
Test name
Test status
Simulation time 22696639 ps
CPU time 0.86 seconds
Started Feb 25 01:57:42 PM PST 24
Finished Feb 25 01:57:43 PM PST 24
Peak memory 218056 kb
Host smart-3c9eb9ed-446d-4779-b2a2-908d30acf5b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087531545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.4087531545 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_alert_test/latest


Test location /workspace/coverage/default/20.kmac_app.3531911710
Short name T240
Test name
Test status
Simulation time 60462780113 ps
CPU time 347.56 seconds
Started Feb 25 01:57:32 PM PST 24
Finished Feb 25 02:03:19 PM PST 24
Peak memory 250012 kb
Host smart-2e6370ef-dc56-42a9-9d34-5ec50ae4b957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531911710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.3531911710 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_app/latest


Test location /workspace/coverage/default/20.kmac_burst_write.3642103362
Short name T894
Test name
Test status
Simulation time 98807647540 ps
CPU time 883.52 seconds
Started Feb 25 01:57:34 PM PST 24
Finished Feb 25 02:12:17 PM PST 24
Peak memory 242952 kb
Host smart-97057990-8921-47c4-918d-15b4c12afec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642103362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.3642103362 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_burst_write/latest


Test location /workspace/coverage/default/20.kmac_entropy_refresh.4251222779
Short name T927
Test name
Test status
Simulation time 8673072191 ps
CPU time 199.27 seconds
Started Feb 25 01:57:35 PM PST 24
Finished Feb 25 02:00:55 PM PST 24
Peak memory 243504 kb
Host smart-2ec38500-e878-4939-ad9e-4b5dadbb7012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251222779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.4251222779 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/20.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/20.kmac_error.534745736
Short name T816
Test name
Test status
Simulation time 8137198302 ps
CPU time 60.88 seconds
Started Feb 25 01:57:34 PM PST 24
Finished Feb 25 01:58:35 PM PST 24
Peak memory 243072 kb
Host smart-193f008e-491f-4b72-b4b8-767f81fd2d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534745736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.534745736 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_error/latest


Test location /workspace/coverage/default/20.kmac_key_error.1816671949
Short name T1043
Test name
Test status
Simulation time 1279601103 ps
CPU time 4.25 seconds
Started Feb 25 01:57:32 PM PST 24
Finished Feb 25 01:57:37 PM PST 24
Peak memory 218296 kb
Host smart-bf72b2b3-379c-42a6-b0cc-4b61845b1164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816671949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.1816671949 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_key_error/latest


Test location /workspace/coverage/default/20.kmac_lc_escalation.2156210808
Short name T18
Test name
Test status
Simulation time 52139069 ps
CPU time 1.6 seconds
Started Feb 25 01:57:33 PM PST 24
Finished Feb 25 01:57:35 PM PST 24
Peak memory 219408 kb
Host smart-3f7f19c5-6602-49e1-b3c2-a1ed23e2fe90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156210808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.2156210808 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/20.kmac_lc_escalation/latest


Test location /workspace/coverage/default/20.kmac_long_msg_and_output.104475707
Short name T494
Test name
Test status
Simulation time 23864444667 ps
CPU time 623.9 seconds
Started Feb 25 01:57:35 PM PST 24
Finished Feb 25 02:07:59 PM PST 24
Peak memory 273480 kb
Host smart-93dcc50a-023b-4721-93a8-712f267eeb72
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104475707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_an
d_output.104475707 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/20.kmac_sideload.3190248884
Short name T273
Test name
Test status
Simulation time 102667132075 ps
CPU time 364.12 seconds
Started Feb 25 01:57:35 PM PST 24
Finished Feb 25 02:03:40 PM PST 24
Peak memory 248320 kb
Host smart-c4b200e5-d2a9-4b70-ad5a-aecbb3d6bef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190248884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.3190248884 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_sideload/latest


Test location /workspace/coverage/default/20.kmac_smoke.644372624
Short name T687
Test name
Test status
Simulation time 16144377075 ps
CPU time 76.44 seconds
Started Feb 25 01:57:33 PM PST 24
Finished Feb 25 01:58:50 PM PST 24
Peak memory 226668 kb
Host smart-e2b28af9-ea7d-47cb-9f03-07b0131957a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644372624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.644372624 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_smoke/latest


Test location /workspace/coverage/default/20.kmac_test_vectors_kmac.2601315836
Short name T289
Test name
Test status
Simulation time 262531104 ps
CPU time 6.51 seconds
Started Feb 25 01:57:32 PM PST 24
Finished Feb 25 01:57:39 PM PST 24
Peak memory 218428 kb
Host smart-91ea429a-72e4-46d2-a357-a80df96a0530
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601315836 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.kmac_test_vectors_kmac.2601315836 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/20.kmac_test_vectors_kmac_xof.1830657269
Short name T712
Test name
Test status
Simulation time 108987822 ps
CPU time 6.78 seconds
Started Feb 25 01:57:35 PM PST 24
Finished Feb 25 01:57:42 PM PST 24
Peak memory 217756 kb
Host smart-513612dc-775f-4e82-9d32-4b7cda9f17bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830657269 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.kmac_test_vectors_kmac_xof.1830657269 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_224.3656351811
Short name T585
Test name
Test status
Simulation time 87051297629 ps
CPU time 2264.22 seconds
Started Feb 25 01:57:33 PM PST 24
Finished Feb 25 02:35:17 PM PST 24
Peak memory 401584 kb
Host smart-034b152d-97d5-4e40-94a9-7912a2030301
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3656351811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_224.3656351811 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_256.3494534399
Short name T377
Test name
Test status
Simulation time 39937077392 ps
CPU time 1967.84 seconds
Started Feb 25 01:57:35 PM PST 24
Finished Feb 25 02:30:23 PM PST 24
Peak memory 389568 kb
Host smart-cb88fac3-ec87-4f7c-98c0-dabf11277070
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3494534399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_256.3494534399 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_384.2035073046
Short name T845
Test name
Test status
Simulation time 31904057232 ps
CPU time 1593.78 seconds
Started Feb 25 01:57:33 PM PST 24
Finished Feb 25 02:24:07 PM PST 24
Peak memory 349288 kb
Host smart-a8bc6a47-1a8a-4806-908e-a29f4a21fd1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2035073046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_384.2035073046 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_512.3863828493
Short name T912
Test name
Test status
Simulation time 55306283701 ps
CPU time 1174.26 seconds
Started Feb 25 01:57:30 PM PST 24
Finished Feb 25 02:17:05 PM PST 24
Peak memory 302112 kb
Host smart-623d0209-6ca7-45d7-bb13-b9508613909f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3863828493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_512.3863828493 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/20.kmac_test_vectors_shake_128.2321869952
Short name T1030
Test name
Test status
Simulation time 2248695210376 ps
CPU time 6744.85 seconds
Started Feb 25 01:57:30 PM PST 24
Finished Feb 25 03:49:56 PM PST 24
Peak memory 651476 kb
Host smart-b4c8ad27-0573-43b0-8578-0f0e92319dda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2321869952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_128.2321869952 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/20.kmac_test_vectors_shake_256.171185365
Short name T220
Test name
Test status
Simulation time 2474442491509 ps
CPU time 5206 seconds
Started Feb 25 01:57:33 PM PST 24
Finished Feb 25 03:24:20 PM PST 24
Peak memory 570312 kb
Host smart-e45b528d-a6db-4c39-ad3f-7925f20b9865
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=171185365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_256.171185365 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/21.kmac_alert_test.260693614
Short name T507
Test name
Test status
Simulation time 17332712 ps
CPU time 0.88 seconds
Started Feb 25 01:57:43 PM PST 24
Finished Feb 25 01:57:44 PM PST 24
Peak memory 218156 kb
Host smart-c4e5c429-47c8-4192-b7af-b8efa420fc78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260693614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.260693614 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/21.kmac_alert_test/latest


Test location /workspace/coverage/default/21.kmac_app.302311250
Short name T204
Test name
Test status
Simulation time 5881746698 ps
CPU time 158.47 seconds
Started Feb 25 01:57:43 PM PST 24
Finished Feb 25 02:00:22 PM PST 24
Peak memory 237996 kb
Host smart-d9531417-8e5b-43fd-92b8-70cbcb1c36fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302311250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.302311250 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_app/latest


Test location /workspace/coverage/default/21.kmac_burst_write.894934882
Short name T425
Test name
Test status
Simulation time 100928186745 ps
CPU time 925.14 seconds
Started Feb 25 01:57:39 PM PST 24
Finished Feb 25 02:13:04 PM PST 24
Peak memory 243032 kb
Host smart-456c996e-cdf2-4923-90fb-e85edfeea3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894934882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.894934882 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_burst_write/latest


Test location /workspace/coverage/default/21.kmac_entropy_refresh.209776645
Short name T316
Test name
Test status
Simulation time 58473655497 ps
CPU time 316.32 seconds
Started Feb 25 01:57:39 PM PST 24
Finished Feb 25 02:02:56 PM PST 24
Peak memory 247808 kb
Host smart-549f458b-5a16-4423-9d68-d6b5221e5f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209776645 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.209776645 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/21.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/21.kmac_error.373939434
Short name T604
Test name
Test status
Simulation time 15614235776 ps
CPU time 76.71 seconds
Started Feb 25 01:57:42 PM PST 24
Finished Feb 25 01:58:59 PM PST 24
Peak memory 240160 kb
Host smart-d416ac2e-f6ed-4e03-8f01-acb0a43acf33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373939434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.373939434 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_error/latest


Test location /workspace/coverage/default/21.kmac_long_msg_and_output.2960554125
Short name T366
Test name
Test status
Simulation time 84147168068 ps
CPU time 2187.1 seconds
Started Feb 25 01:57:39 PM PST 24
Finished Feb 25 02:34:07 PM PST 24
Peak memory 415708 kb
Host smart-8397653b-bc87-4041-93b3-5cc1dbfa41eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960554125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_a
nd_output.2960554125 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/21.kmac_sideload.2559042329
Short name T913
Test name
Test status
Simulation time 101710672957 ps
CPU time 582.61 seconds
Started Feb 25 01:57:39 PM PST 24
Finished Feb 25 02:07:22 PM PST 24
Peak memory 255020 kb
Host smart-8b01266e-34ba-45c7-9cba-4b6c8d805598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559042329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.2559042329 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_sideload/latest


Test location /workspace/coverage/default/21.kmac_smoke.4116927098
Short name T933
Test name
Test status
Simulation time 2392919993 ps
CPU time 5.6 seconds
Started Feb 25 01:57:42 PM PST 24
Finished Feb 25 01:57:48 PM PST 24
Peak memory 226616 kb
Host smart-a510fe89-7c10-46f0-ba8a-d79ec62234f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116927098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.4116927098 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_smoke/latest


Test location /workspace/coverage/default/21.kmac_stress_all.995081712
Short name T559
Test name
Test status
Simulation time 58866992345 ps
CPU time 2180.95 seconds
Started Feb 25 01:57:39 PM PST 24
Finished Feb 25 02:34:00 PM PST 24
Peak memory 385976 kb
Host smart-b7945bd6-e5ad-4cc2-a279-be42954a4258
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=995081712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.995081712 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_stress_all/latest


Test location /workspace/coverage/default/21.kmac_test_vectors_kmac.2232927780
Short name T774
Test name
Test status
Simulation time 381525204 ps
CPU time 6.41 seconds
Started Feb 25 01:57:39 PM PST 24
Finished Feb 25 01:57:45 PM PST 24
Peak memory 219788 kb
Host smart-b8dec15e-b74b-4fe2-bfd7-82871bfe3bd1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232927780 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.kmac_test_vectors_kmac.2232927780 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/21.kmac_test_vectors_kmac_xof.1041558868
Short name T368
Test name
Test status
Simulation time 170203838 ps
CPU time 6.06 seconds
Started Feb 25 01:57:40 PM PST 24
Finished Feb 25 01:57:46 PM PST 24
Peak memory 219832 kb
Host smart-9ec95e32-00e6-49bb-8754-56e1ca835a62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041558868 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.kmac_test_vectors_kmac_xof.1041558868 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_224.149854026
Short name T193
Test name
Test status
Simulation time 66729790364 ps
CPU time 2281.07 seconds
Started Feb 25 01:57:39 PM PST 24
Finished Feb 25 02:35:40 PM PST 24
Peak memory 393812 kb
Host smart-b00fa0ee-dcf9-48ce-9b7d-f243c566bef4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=149854026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_224.149854026 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_256.4276138880
Short name T498
Test name
Test status
Simulation time 435907098133 ps
CPU time 2287.44 seconds
Started Feb 25 01:57:41 PM PST 24
Finished Feb 25 02:35:49 PM PST 24
Peak memory 382956 kb
Host smart-da743c4f-97c0-4ef3-9aef-f5c0826532bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4276138880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_256.4276138880 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_384.1743387350
Short name T707
Test name
Test status
Simulation time 297662737695 ps
CPU time 1952.07 seconds
Started Feb 25 01:57:41 PM PST 24
Finished Feb 25 02:30:13 PM PST 24
Peak memory 340948 kb
Host smart-723ea9b6-0a7f-41e2-a7a9-454d72debf44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1743387350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_384.1743387350 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_512.3002667273
Short name T611
Test name
Test status
Simulation time 22152074145 ps
CPU time 1341.52 seconds
Started Feb 25 01:57:39 PM PST 24
Finished Feb 25 02:20:01 PM PST 24
Peak memory 302376 kb
Host smart-c08544bb-8e52-431a-8885-9cc56a8a0296
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3002667273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_512.3002667273 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/21.kmac_test_vectors_shake_128.103291091
Short name T30
Test name
Test status
Simulation time 242923337391 ps
CPU time 5397.27 seconds
Started Feb 25 01:57:39 PM PST 24
Finished Feb 25 03:27:37 PM PST 24
Peak memory 675292 kb
Host smart-06e8763f-cbd7-4c9e-9a2d-6f58943172ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=103291091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_128.103291091 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/21.kmac_test_vectors_shake_256.2560205718
Short name T538
Test name
Test status
Simulation time 203476162712 ps
CPU time 4068.41 seconds
Started Feb 25 01:57:42 PM PST 24
Finished Feb 25 03:05:31 PM PST 24
Peak memory 574696 kb
Host smart-df5b6410-ae52-4060-907c-9ed35d7362c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2560205718 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_256.2560205718 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/22.kmac_alert_test.1600569442
Short name T636
Test name
Test status
Simulation time 23976403 ps
CPU time 0.93 seconds
Started Feb 25 01:58:04 PM PST 24
Finished Feb 25 01:58:05 PM PST 24
Peak memory 218160 kb
Host smart-7050334a-997b-4c81-9971-37bbe731884c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600569442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.1600569442 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_alert_test/latest


Test location /workspace/coverage/default/22.kmac_app.3529656171
Short name T297
Test name
Test status
Simulation time 1605551254 ps
CPU time 87.29 seconds
Started Feb 25 01:58:06 PM PST 24
Finished Feb 25 01:59:33 PM PST 24
Peak memory 243028 kb
Host smart-db5127f5-dfaa-46df-b563-65aeb72b1ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529656171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.3529656171 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_app/latest


Test location /workspace/coverage/default/22.kmac_burst_write.3673693846
Short name T599
Test name
Test status
Simulation time 17672982547 ps
CPU time 714.13 seconds
Started Feb 25 01:57:48 PM PST 24
Finished Feb 25 02:09:42 PM PST 24
Peak memory 243024 kb
Host smart-86ca6032-1001-4e3c-9c9b-7f79a5894d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673693846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.3673693846 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_burst_write/latest


Test location /workspace/coverage/default/22.kmac_entropy_refresh.529377384
Short name T843
Test name
Test status
Simulation time 147674837 ps
CPU time 5.24 seconds
Started Feb 25 01:58:05 PM PST 24
Finished Feb 25 01:58:11 PM PST 24
Peak memory 221280 kb
Host smart-5fbb5a4a-c467-4964-83fc-065c92fe5554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529377384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.529377384 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/22.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/22.kmac_error.116945640
Short name T579
Test name
Test status
Simulation time 7823582807 ps
CPU time 141.75 seconds
Started Feb 25 01:58:05 PM PST 24
Finished Feb 25 02:00:27 PM PST 24
Peak memory 259440 kb
Host smart-cf1a040c-7400-47fd-83bf-1b7b1fd792da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116945640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.116945640 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_error/latest


Test location /workspace/coverage/default/22.kmac_key_error.2317101120
Short name T608
Test name
Test status
Simulation time 1226432407 ps
CPU time 2.91 seconds
Started Feb 25 01:58:06 PM PST 24
Finished Feb 25 01:58:09 PM PST 24
Peak memory 218296 kb
Host smart-ea0d780e-6747-4ec8-9ffe-464bfe80a099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317101120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.2317101120 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_key_error/latest


Test location /workspace/coverage/default/22.kmac_lc_escalation.195250411
Short name T609
Test name
Test status
Simulation time 40226394 ps
CPU time 1.46 seconds
Started Feb 25 01:58:03 PM PST 24
Finished Feb 25 01:58:04 PM PST 24
Peak memory 220384 kb
Host smart-f463075c-5cfd-48af-b984-060961fc7bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195250411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.195250411 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/22.kmac_lc_escalation/latest


Test location /workspace/coverage/default/22.kmac_long_msg_and_output.1533141514
Short name T1007
Test name
Test status
Simulation time 41951665038 ps
CPU time 400.98 seconds
Started Feb 25 01:57:49 PM PST 24
Finished Feb 25 02:04:30 PM PST 24
Peak memory 251888 kb
Host smart-d97da6a5-8eda-4359-a596-939b09b4f752
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533141514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_a
nd_output.1533141514 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/22.kmac_sideload.1277486779
Short name T249
Test name
Test status
Simulation time 30868251804 ps
CPU time 411.81 seconds
Started Feb 25 01:57:51 PM PST 24
Finished Feb 25 02:04:43 PM PST 24
Peak memory 251708 kb
Host smart-d3cbd309-6855-42d7-ae9c-987cc7e5edc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277486779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.1277486779 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_sideload/latest


Test location /workspace/coverage/default/22.kmac_smoke.2524611026
Short name T1057
Test name
Test status
Simulation time 5636330079 ps
CPU time 67.33 seconds
Started Feb 25 01:57:48 PM PST 24
Finished Feb 25 01:58:56 PM PST 24
Peak memory 223964 kb
Host smart-4b99a2de-8d36-472b-b31b-bc11aa0a8972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524611026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.2524611026 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_smoke/latest


Test location /workspace/coverage/default/22.kmac_test_vectors_kmac.445487819
Short name T1048
Test name
Test status
Simulation time 1114052122 ps
CPU time 6.8 seconds
Started Feb 25 01:57:49 PM PST 24
Finished Feb 25 01:57:56 PM PST 24
Peak memory 219816 kb
Host smart-f4d452d1-4bca-43b7-9911-732cf9b75796
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445487819 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.kmac_test_vectors_kmac.445487819 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/22.kmac_test_vectors_kmac_xof.3990326957
Short name T413
Test name
Test status
Simulation time 246106082 ps
CPU time 5.7 seconds
Started Feb 25 01:58:06 PM PST 24
Finished Feb 25 01:58:11 PM PST 24
Peak memory 218396 kb
Host smart-3ca884da-0454-40bf-9747-4a5c824b05ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990326957 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.kmac_test_vectors_kmac_xof.3990326957 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_224.1344346181
Short name T1015
Test name
Test status
Simulation time 390485754272 ps
CPU time 2451.68 seconds
Started Feb 25 01:57:47 PM PST 24
Finished Feb 25 02:38:39 PM PST 24
Peak memory 399800 kb
Host smart-d67fb165-0bdd-46d9-a4c8-cda67c3e2307
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1344346181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_224.1344346181 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_256.2624801797
Short name T743
Test name
Test status
Simulation time 194286155922 ps
CPU time 2282.66 seconds
Started Feb 25 01:57:47 PM PST 24
Finished Feb 25 02:35:50 PM PST 24
Peak memory 387304 kb
Host smart-b7e83922-7fae-486a-88e8-2c10cb71505d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2624801797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_256.2624801797 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_384.3807903268
Short name T877
Test name
Test status
Simulation time 61642021409 ps
CPU time 1628.72 seconds
Started Feb 25 01:57:48 PM PST 24
Finished Feb 25 02:24:57 PM PST 24
Peak memory 338232 kb
Host smart-d12f7351-15a2-4196-8768-c19492f45869
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3807903268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_384.3807903268 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_512.315502896
Short name T645
Test name
Test status
Simulation time 21315601413 ps
CPU time 1337.24 seconds
Started Feb 25 01:57:51 PM PST 24
Finished Feb 25 02:20:09 PM PST 24
Peak memory 305396 kb
Host smart-6b6e55fa-7ba5-4fe1-899f-8dfde720af1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=315502896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_512.315502896 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/22.kmac_test_vectors_shake_128.1990296056
Short name T445
Test name
Test status
Simulation time 716052721673 ps
CPU time 6315.34 seconds
Started Feb 25 01:57:50 PM PST 24
Finished Feb 25 03:43:06 PM PST 24
Peak memory 665168 kb
Host smart-8d8903fd-3129-40c3-9905-9738a48118e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1990296056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_128.1990296056 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/22.kmac_test_vectors_shake_256.676671371
Short name T31
Test name
Test status
Simulation time 1160088097917 ps
CPU time 5590.54 seconds
Started Feb 25 01:57:47 PM PST 24
Finished Feb 25 03:30:59 PM PST 24
Peak memory 571660 kb
Host smart-2eb89e6f-427c-4754-912b-0f5ac73aa7d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=676671371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_256.676671371 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/23.kmac_alert_test.3742614735
Short name T497
Test name
Test status
Simulation time 19324975 ps
CPU time 0.88 seconds
Started Feb 25 01:58:13 PM PST 24
Finished Feb 25 01:58:14 PM PST 24
Peak memory 219264 kb
Host smart-a7012977-7829-4665-b8b9-97a492eaa593
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742614735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.3742614735 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_alert_test/latest


Test location /workspace/coverage/default/23.kmac_app.2769492358
Short name T362
Test name
Test status
Simulation time 3288345687 ps
CPU time 90.42 seconds
Started Feb 25 01:58:10 PM PST 24
Finished Feb 25 01:59:41 PM PST 24
Peak memory 233160 kb
Host smart-608aec9a-2d99-429f-ae05-426cdc781545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769492358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.2769492358 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_app/latest


Test location /workspace/coverage/default/23.kmac_burst_write.198340107
Short name T270
Test name
Test status
Simulation time 15970544075 ps
CPU time 257.83 seconds
Started Feb 25 01:58:02 PM PST 24
Finished Feb 25 02:02:20 PM PST 24
Peak memory 239852 kb
Host smart-91dee540-16be-4e14-83b9-a1146ccf6c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198340107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.198340107 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_burst_write/latest


Test location /workspace/coverage/default/23.kmac_entropy_refresh.3388121825
Short name T44
Test name
Test status
Simulation time 1840437347 ps
CPU time 121.93 seconds
Started Feb 25 01:58:15 PM PST 24
Finished Feb 25 02:00:17 PM PST 24
Peak memory 236632 kb
Host smart-23e240b7-1f59-4a75-9200-b53b9600d74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388121825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.3388121825 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/23.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/23.kmac_error.4026595123
Short name T666
Test name
Test status
Simulation time 81151873801 ps
CPU time 428.9 seconds
Started Feb 25 01:58:13 PM PST 24
Finished Feb 25 02:05:22 PM PST 24
Peak memory 267672 kb
Host smart-a326c718-0bf2-46e9-a225-bf547337d7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026595123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.4026595123 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_error/latest


Test location /workspace/coverage/default/23.kmac_key_error.2067331951
Short name T1012
Test name
Test status
Simulation time 419592274 ps
CPU time 1.09 seconds
Started Feb 25 01:58:11 PM PST 24
Finished Feb 25 01:58:13 PM PST 24
Peak memory 218168 kb
Host smart-6d9ae74b-1f31-4e91-ad36-05c82b32728a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067331951 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.2067331951 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_key_error/latest


Test location /workspace/coverage/default/23.kmac_lc_escalation.1281467871
Short name T22
Test name
Test status
Simulation time 39124206 ps
CPU time 1.39 seconds
Started Feb 25 01:58:12 PM PST 24
Finished Feb 25 01:58:13 PM PST 24
Peak memory 218424 kb
Host smart-33f9bebb-eece-4ada-95bd-26663fc61ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281467871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.1281467871 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/23.kmac_lc_escalation/latest


Test location /workspace/coverage/default/23.kmac_long_msg_and_output.1485819638
Short name T314
Test name
Test status
Simulation time 673188236936 ps
CPU time 3288.55 seconds
Started Feb 25 01:58:02 PM PST 24
Finished Feb 25 02:52:51 PM PST 24
Peak memory 445372 kb
Host smart-3fc63659-cd6d-4b24-9651-10d501b19cf9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485819638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_a
nd_output.1485819638 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/23.kmac_sideload.3355696328
Short name T407
Test name
Test status
Simulation time 21587917811 ps
CPU time 444.54 seconds
Started Feb 25 01:58:03 PM PST 24
Finished Feb 25 02:05:28 PM PST 24
Peak memory 254596 kb
Host smart-4dc5e524-8d56-4f37-9505-8ec244173857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355696328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.3355696328 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_sideload/latest


Test location /workspace/coverage/default/23.kmac_smoke.369396790
Short name T739
Test name
Test status
Simulation time 6722681259 ps
CPU time 69.39 seconds
Started Feb 25 01:58:03 PM PST 24
Finished Feb 25 01:59:13 PM PST 24
Peak memory 226676 kb
Host smart-d3773e82-adad-45bc-852b-553b3874395b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369396790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.369396790 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_smoke/latest


Test location /workspace/coverage/default/23.kmac_stress_all.3268059621
Short name T535
Test name
Test status
Simulation time 4370591877 ps
CPU time 251.01 seconds
Started Feb 25 01:58:12 PM PST 24
Finished Feb 25 02:02:24 PM PST 24
Peak memory 268908 kb
Host smart-839a57fd-eb0d-436e-8b99-2c43a16ad85c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3268059621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.3268059621 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_stress_all/latest


Test location /workspace/coverage/default/23.kmac_test_vectors_kmac.2218365614
Short name T163
Test name
Test status
Simulation time 3318736175 ps
CPU time 6.72 seconds
Started Feb 25 01:58:11 PM PST 24
Finished Feb 25 01:58:18 PM PST 24
Peak memory 219936 kb
Host smart-6bec1d34-e4f6-416c-a012-9149bc34f588
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218365614 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.kmac_test_vectors_kmac.2218365614 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/23.kmac_test_vectors_kmac_xof.289177189
Short name T213
Test name
Test status
Simulation time 258277505 ps
CPU time 6.43 seconds
Started Feb 25 01:58:11 PM PST 24
Finished Feb 25 01:58:17 PM PST 24
Peak memory 218380 kb
Host smart-87961a94-56fa-4c70-b5ab-cd98fa0d8799
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289177189 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.kmac_test_vectors_kmac_xof.289177189 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_224.2053824369
Short name T1025
Test name
Test status
Simulation time 42258634609 ps
CPU time 1979.81 seconds
Started Feb 25 01:58:08 PM PST 24
Finished Feb 25 02:31:08 PM PST 24
Peak memory 397396 kb
Host smart-3720a4c5-018b-4dc3-b4d7-763888d9b6d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2053824369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_224.2053824369 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_256.426378976
Short name T646
Test name
Test status
Simulation time 248884438095 ps
CPU time 2163.01 seconds
Started Feb 25 01:58:02 PM PST 24
Finished Feb 25 02:34:06 PM PST 24
Peak memory 390196 kb
Host smart-07221ff7-ab52-4526-b505-48e3613d7c9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=426378976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_256.426378976 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_384.1754947326
Short name T960
Test name
Test status
Simulation time 47223841064 ps
CPU time 1817.47 seconds
Started Feb 25 01:58:01 PM PST 24
Finished Feb 25 02:28:19 PM PST 24
Peak memory 339852 kb
Host smart-b530b655-6c22-4900-813c-a9b46f99dac7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1754947326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_384.1754947326 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_512.2644975002
Short name T940
Test name
Test status
Simulation time 89972760240 ps
CPU time 1321.1 seconds
Started Feb 25 01:58:10 PM PST 24
Finished Feb 25 02:20:11 PM PST 24
Peak memory 303660 kb
Host smart-3fe41a2a-ace8-47e8-b290-e25f52440dee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2644975002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_512.2644975002 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/23.kmac_test_vectors_shake_128.1869692193
Short name T853
Test name
Test status
Simulation time 123532157511 ps
CPU time 5295.61 seconds
Started Feb 25 01:58:09 PM PST 24
Finished Feb 25 03:26:26 PM PST 24
Peak memory 643708 kb
Host smart-b4a0cdb6-90c5-4d47-99a0-ce27b773c2ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1869692193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_128.1869692193 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/23.kmac_test_vectors_shake_256.2099924938
Short name T951
Test name
Test status
Simulation time 155519550097 ps
CPU time 4927.34 seconds
Started Feb 25 01:58:15 PM PST 24
Finished Feb 25 03:20:23 PM PST 24
Peak memory 573696 kb
Host smart-96d2521e-24f8-4a6e-aa42-99211c448eaa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2099924938 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_256.2099924938 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/24.kmac_alert_test.2656470893
Short name T364
Test name
Test status
Simulation time 288154988 ps
CPU time 0.93 seconds
Started Feb 25 01:58:25 PM PST 24
Finished Feb 25 01:58:26 PM PST 24
Peak memory 219300 kb
Host smart-fb626fbc-59ce-41f7-b737-3d6fa8f90955
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656470893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.2656470893 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_alert_test/latest


Test location /workspace/coverage/default/24.kmac_app.1801300491
Short name T12
Test name
Test status
Simulation time 2107983295 ps
CPU time 29.06 seconds
Started Feb 25 01:58:24 PM PST 24
Finished Feb 25 01:58:53 PM PST 24
Peak memory 224200 kb
Host smart-12f42cba-8de8-430a-8208-c84f81b38039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801300491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.1801300491 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_app/latest


Test location /workspace/coverage/default/24.kmac_error.2998380869
Short name T690
Test name
Test status
Simulation time 5885253474 ps
CPU time 76.91 seconds
Started Feb 25 01:58:23 PM PST 24
Finished Feb 25 01:59:41 PM PST 24
Peak memory 243016 kb
Host smart-2092474e-5739-45d8-93c8-a03f45e71a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998380869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.2998380869 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_error/latest


Test location /workspace/coverage/default/24.kmac_lc_escalation.2584356445
Short name T923
Test name
Test status
Simulation time 732719811 ps
CPU time 13.59 seconds
Started Feb 25 01:58:23 PM PST 24
Finished Feb 25 01:58:37 PM PST 24
Peak memory 229512 kb
Host smart-3cf8ff62-fafa-4807-ba1a-a36a659fc37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584356445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.2584356445 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/24.kmac_lc_escalation/latest


Test location /workspace/coverage/default/24.kmac_long_msg_and_output.3976821854
Short name T1021
Test name
Test status
Simulation time 9677266275 ps
CPU time 396.53 seconds
Started Feb 25 01:58:12 PM PST 24
Finished Feb 25 02:04:48 PM PST 24
Peak memory 253388 kb
Host smart-9b4e5067-8e70-4996-8030-3b3f898cbebb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976821854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_a
nd_output.3976821854 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/24.kmac_sideload.3783471592
Short name T814
Test name
Test status
Simulation time 2275856343 ps
CPU time 127.1 seconds
Started Feb 25 01:58:15 PM PST 24
Finished Feb 25 02:00:22 PM PST 24
Peak memory 235296 kb
Host smart-e7ba219d-2665-437e-9122-be3861b1bd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783471592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.3783471592 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_sideload/latest


Test location /workspace/coverage/default/24.kmac_smoke.3673989591
Short name T771
Test name
Test status
Simulation time 809861892 ps
CPU time 16.87 seconds
Started Feb 25 01:58:17 PM PST 24
Finished Feb 25 01:58:34 PM PST 24
Peak memory 222592 kb
Host smart-4b89f01d-73a9-4e1d-b326-8e3d306c9d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673989591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.3673989591 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_smoke/latest


Test location /workspace/coverage/default/24.kmac_stress_all.1699733954
Short name T4
Test name
Test status
Simulation time 9086012979 ps
CPU time 189.55 seconds
Started Feb 25 01:58:30 PM PST 24
Finished Feb 25 02:01:40 PM PST 24
Peak memory 259164 kb
Host smart-718f26ba-a489-49fb-a048-fb98f37f6f02
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1699733954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.1699733954 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_stress_all/latest


Test location /workspace/coverage/default/24.kmac_test_vectors_kmac.1240689257
Short name T437
Test name
Test status
Simulation time 236872517 ps
CPU time 6.5 seconds
Started Feb 25 01:58:24 PM PST 24
Finished Feb 25 01:58:30 PM PST 24
Peak memory 219820 kb
Host smart-fb0a27b3-ad08-4b2b-955d-8bc37d1c337e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240689257 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.kmac_test_vectors_kmac.1240689257 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/24.kmac_test_vectors_kmac_xof.1524190873
Short name T964
Test name
Test status
Simulation time 91461779 ps
CPU time 6.26 seconds
Started Feb 25 01:58:22 PM PST 24
Finished Feb 25 01:58:29 PM PST 24
Peak memory 218364 kb
Host smart-5c1c7b53-9ebe-4e76-ba7b-13b0c58d7987
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524190873 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.kmac_test_vectors_kmac_xof.1524190873 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_224.3045993146
Short name T555
Test name
Test status
Simulation time 63612827158 ps
CPU time 2368.08 seconds
Started Feb 25 01:58:13 PM PST 24
Finished Feb 25 02:37:42 PM PST 24
Peak memory 387060 kb
Host smart-48f54196-4ada-40f6-b340-0fa4561ddb41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3045993146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_224.3045993146 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_256.444961334
Short name T157
Test name
Test status
Simulation time 246559949611 ps
CPU time 2321 seconds
Started Feb 25 01:58:12 PM PST 24
Finished Feb 25 02:36:53 PM PST 24
Peak memory 385164 kb
Host smart-46b05dd3-ac32-47b9-8801-d71b992dfa31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=444961334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_256.444961334 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_384.1751961763
Short name T285
Test name
Test status
Simulation time 29367373221 ps
CPU time 1608.18 seconds
Started Feb 25 01:58:20 PM PST 24
Finished Feb 25 02:25:08 PM PST 24
Peak memory 338500 kb
Host smart-e870508f-01c2-42c4-abe4-e091c4b578ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1751961763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_384.1751961763 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_512.3173729023
Short name T986
Test name
Test status
Simulation time 616820962635 ps
CPU time 1596.46 seconds
Started Feb 25 01:58:13 PM PST 24
Finished Feb 25 02:24:50 PM PST 24
Peak memory 303024 kb
Host smart-592cfc2d-5c26-49e2-b78e-535f0a31327e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3173729023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_512.3173729023 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/24.kmac_test_vectors_shake_128.2676403683
Short name T290
Test name
Test status
Simulation time 533570647050 ps
CPU time 6636.73 seconds
Started Feb 25 01:58:15 PM PST 24
Finished Feb 25 03:48:53 PM PST 24
Peak memory 646676 kb
Host smart-02ca5c75-091f-45f0-9155-deb0ca76ef41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2676403683 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_128.2676403683 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/24.kmac_test_vectors_shake_256.2054804555
Short name T442
Test name
Test status
Simulation time 313427855136 ps
CPU time 5308.7 seconds
Started Feb 25 01:58:24 PM PST 24
Finished Feb 25 03:26:54 PM PST 24
Peak memory 578696 kb
Host smart-cdc7eaec-c443-41df-8344-660bc9491500
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2054804555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_256.2054804555 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/25.kmac_alert_test.4041025734
Short name T386
Test name
Test status
Simulation time 15101898 ps
CPU time 0.83 seconds
Started Feb 25 01:58:31 PM PST 24
Finished Feb 25 01:58:34 PM PST 24
Peak memory 219304 kb
Host smart-52d60a9e-c55b-4206-a2a7-151aaaee4221
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041025734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.4041025734 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_alert_test/latest


Test location /workspace/coverage/default/25.kmac_app.3930118021
Short name T643
Test name
Test status
Simulation time 62515415907 ps
CPU time 456.97 seconds
Started Feb 25 01:58:23 PM PST 24
Finished Feb 25 02:06:00 PM PST 24
Peak memory 252560 kb
Host smart-1a5814d1-0a3b-43e2-b146-3b1ea9f21281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930118021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.3930118021 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_app/latest


Test location /workspace/coverage/default/25.kmac_burst_write.2998870622
Short name T868
Test name
Test status
Simulation time 28741310591 ps
CPU time 273.84 seconds
Started Feb 25 01:58:21 PM PST 24
Finished Feb 25 02:02:56 PM PST 24
Peak memory 239520 kb
Host smart-d9ac6dfd-a560-40dc-9ba7-e9ee4c681ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998870622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.2998870622 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_burst_write/latest


Test location /workspace/coverage/default/25.kmac_entropy_refresh.2426217773
Short name T288
Test name
Test status
Simulation time 5335975969 ps
CPU time 217.56 seconds
Started Feb 25 01:58:25 PM PST 24
Finished Feb 25 02:02:03 PM PST 24
Peak memory 244288 kb
Host smart-99b9edfe-384a-44f2-8ad6-3116210677a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426217773 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.2426217773 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/25.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/25.kmac_error.2888552424
Short name T46
Test name
Test status
Simulation time 15467045747 ps
CPU time 343.04 seconds
Started Feb 25 01:58:23 PM PST 24
Finished Feb 25 02:04:06 PM PST 24
Peak memory 259072 kb
Host smart-afe48f13-736f-4db2-962b-82b176eb93f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888552424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.2888552424 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_error/latest


Test location /workspace/coverage/default/25.kmac_key_error.2498238040
Short name T1059
Test name
Test status
Simulation time 11086846364 ps
CPU time 7.5 seconds
Started Feb 25 01:58:24 PM PST 24
Finished Feb 25 01:58:31 PM PST 24
Peak memory 218432 kb
Host smart-28a0de88-25fb-4164-bf54-2bd2b9552902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498238040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.2498238040 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_key_error/latest


Test location /workspace/coverage/default/25.kmac_lc_escalation.3557656198
Short name T19
Test name
Test status
Simulation time 58267867 ps
CPU time 1.59 seconds
Started Feb 25 01:58:27 PM PST 24
Finished Feb 25 01:58:28 PM PST 24
Peak memory 219404 kb
Host smart-3b302745-d7ba-4890-88af-4057921c0191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557656198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.3557656198 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/25.kmac_lc_escalation/latest


Test location /workspace/coverage/default/25.kmac_long_msg_and_output.463847401
Short name T114
Test name
Test status
Simulation time 16418780447 ps
CPU time 1893.23 seconds
Started Feb 25 01:58:24 PM PST 24
Finished Feb 25 02:29:58 PM PST 24
Peak memory 377824 kb
Host smart-d1346533-af5a-48c0-a066-b28db01da380
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463847401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_an
d_output.463847401 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/25.kmac_sideload.3386647394
Short name T617
Test name
Test status
Simulation time 9353655842 ps
CPU time 273.34 seconds
Started Feb 25 01:58:24 PM PST 24
Finished Feb 25 02:02:57 PM PST 24
Peak memory 243332 kb
Host smart-ce6b528e-f1b2-4249-9a4d-bbddb3e6668b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386647394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.3386647394 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_sideload/latest


Test location /workspace/coverage/default/25.kmac_smoke.1317435765
Short name T827
Test name
Test status
Simulation time 2793083789 ps
CPU time 57.37 seconds
Started Feb 25 01:58:22 PM PST 24
Finished Feb 25 01:59:20 PM PST 24
Peak memory 223912 kb
Host smart-e6f4c9ea-65f4-4dff-8ef7-9bdcecaf5166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317435765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.1317435765 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_smoke/latest


Test location /workspace/coverage/default/25.kmac_stress_all.3657347126
Short name T563
Test name
Test status
Simulation time 134571397420 ps
CPU time 2612.09 seconds
Started Feb 25 01:58:25 PM PST 24
Finished Feb 25 02:41:58 PM PST 24
Peak memory 451960 kb
Host smart-600080e0-d261-400c-bd9f-98770d910265
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3657347126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.3657347126 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_stress_all/latest


Test location /workspace/coverage/default/25.kmac_stress_all_with_rand_reset.1149690604
Short name T65
Test name
Test status
Simulation time 23617909380 ps
CPU time 834.2 seconds
Started Feb 25 01:58:28 PM PST 24
Finished Feb 25 02:12:23 PM PST 24
Peak memory 292248 kb
Host smart-ddb43ad7-6b47-462e-ad44-fb03a546c0eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1149690604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all_with_rand_reset.1149690604 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/25.kmac_test_vectors_kmac.371792334
Short name T562
Test name
Test status
Simulation time 442224136 ps
CPU time 6.07 seconds
Started Feb 25 01:58:26 PM PST 24
Finished Feb 25 01:58:33 PM PST 24
Peak memory 220144 kb
Host smart-06faa69d-dce7-4e98-862c-c9d4d3bfe646
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371792334 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.kmac_test_vectors_kmac.371792334 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/25.kmac_test_vectors_kmac_xof.1181380350
Short name T422
Test name
Test status
Simulation time 774461154 ps
CPU time 5.86 seconds
Started Feb 25 01:58:24 PM PST 24
Finished Feb 25 01:58:30 PM PST 24
Peak memory 219416 kb
Host smart-54be8447-9480-4870-b2fd-2aeb0577d758
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181380350 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.kmac_test_vectors_kmac_xof.1181380350 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_224.607670631
Short name T263
Test name
Test status
Simulation time 99292279520 ps
CPU time 2357.14 seconds
Started Feb 25 01:58:25 PM PST 24
Finished Feb 25 02:37:43 PM PST 24
Peak memory 391732 kb
Host smart-26343fab-346d-494f-b373-3cf2b8cef6ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=607670631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_224.607670631 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_256.1368012069
Short name T409
Test name
Test status
Simulation time 346678706248 ps
CPU time 2539.41 seconds
Started Feb 25 01:58:23 PM PST 24
Finished Feb 25 02:40:43 PM PST 24
Peak memory 391364 kb
Host smart-2cc153d4-5a98-4058-835f-18533d79edc7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1368012069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_256.1368012069 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_384.842406142
Short name T361
Test name
Test status
Simulation time 32673534876 ps
CPU time 1622.85 seconds
Started Feb 25 01:58:23 PM PST 24
Finished Feb 25 02:25:26 PM PST 24
Peak memory 342172 kb
Host smart-ed26d7f3-dd6d-40b3-9a03-6ba880d03112
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=842406142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_384.842406142 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_512.3338770807
Short name T212
Test name
Test status
Simulation time 42783513243 ps
CPU time 1160.34 seconds
Started Feb 25 01:58:31 PM PST 24
Finished Feb 25 02:17:53 PM PST 24
Peak memory 296044 kb
Host smart-1c6ac082-69e2-4453-b5bb-e819c8b6dd4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3338770807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_512.3338770807 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/25.kmac_test_vectors_shake_128.2590701671
Short name T745
Test name
Test status
Simulation time 314362258413 ps
CPU time 5444.98 seconds
Started Feb 25 01:58:24 PM PST 24
Finished Feb 25 03:29:10 PM PST 24
Peak memory 648124 kb
Host smart-2857629a-f2ea-4bcf-900a-39c81e72b00b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2590701671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_128.2590701671 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/25.kmac_test_vectors_shake_256.1323061459
Short name T412
Test name
Test status
Simulation time 115228287783 ps
CPU time 4432.49 seconds
Started Feb 25 01:58:26 PM PST 24
Finished Feb 25 03:12:20 PM PST 24
Peak memory 569708 kb
Host smart-28681ae4-27a1-48d2-a874-e84dafe2096c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1323061459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_256.1323061459 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/26.kmac_alert_test.2186315515
Short name T551
Test name
Test status
Simulation time 28095237 ps
CPU time 0.85 seconds
Started Feb 25 01:58:41 PM PST 24
Finished Feb 25 01:58:42 PM PST 24
Peak memory 219320 kb
Host smart-d2c7b559-4290-4c51-8301-da22221f3898
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186315515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.2186315515 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_alert_test/latest


Test location /workspace/coverage/default/26.kmac_app.3896600315
Short name T443
Test name
Test status
Simulation time 7338434625 ps
CPU time 126.12 seconds
Started Feb 25 01:58:36 PM PST 24
Finished Feb 25 02:00:43 PM PST 24
Peak memory 237632 kb
Host smart-790fa030-f15e-4d99-8845-614c9f9c66bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896600315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.3896600315 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_app/latest


Test location /workspace/coverage/default/26.kmac_burst_write.9471738
Short name T782
Test name
Test status
Simulation time 2461781958 ps
CPU time 56.25 seconds
Started Feb 25 01:58:28 PM PST 24
Finished Feb 25 01:59:25 PM PST 24
Peak memory 233520 kb
Host smart-37636290-863a-419d-becc-c5eb3ac41461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9471738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.9471738 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_burst_write/latest


Test location /workspace/coverage/default/26.kmac_entropy_refresh.2942842449
Short name T390
Test name
Test status
Simulation time 297210614 ps
CPU time 5.34 seconds
Started Feb 25 01:58:36 PM PST 24
Finished Feb 25 01:58:42 PM PST 24
Peak memory 219248 kb
Host smart-908a37b0-9db5-4819-9e8f-1d9c1c0e9097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942842449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.2942842449 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/26.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/26.kmac_error.215297025
Short name T10
Test name
Test status
Simulation time 5149750481 ps
CPU time 105.53 seconds
Started Feb 25 01:58:32 PM PST 24
Finished Feb 25 02:00:18 PM PST 24
Peak memory 243388 kb
Host smart-ea1aa36b-5994-4ba2-9d9e-c22aa2a9aaf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215297025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.215297025 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_error/latest


Test location /workspace/coverage/default/26.kmac_key_error.84437074
Short name T728
Test name
Test status
Simulation time 2247508504 ps
CPU time 3.79 seconds
Started Feb 25 01:58:32 PM PST 24
Finished Feb 25 01:58:36 PM PST 24
Peak memory 218336 kb
Host smart-dde7e72c-f7d2-40cb-9ef8-c2d31f0cfb07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84437074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.84437074 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_key_error/latest


Test location /workspace/coverage/default/26.kmac_lc_escalation.2345049460
Short name T60
Test name
Test status
Simulation time 68961815 ps
CPU time 1.4 seconds
Started Feb 25 01:58:32 PM PST 24
Finished Feb 25 01:58:34 PM PST 24
Peak memory 219652 kb
Host smart-c53435a9-539b-4861-bb70-94ff695c60bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345049460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.2345049460 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/26.kmac_lc_escalation/latest


Test location /workspace/coverage/default/26.kmac_long_msg_and_output.1617966425
Short name T700
Test name
Test status
Simulation time 445809736724 ps
CPU time 2647.03 seconds
Started Feb 25 01:58:36 PM PST 24
Finished Feb 25 02:42:44 PM PST 24
Peak memory 408476 kb
Host smart-c4aedc82-609c-4995-bfc3-22d0f06da531
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617966425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_a
nd_output.1617966425 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/26.kmac_sideload.410126612
Short name T658
Test name
Test status
Simulation time 19863412803 ps
CPU time 379.08 seconds
Started Feb 25 01:58:29 PM PST 24
Finished Feb 25 02:04:49 PM PST 24
Peak memory 249880 kb
Host smart-79b249b5-4a23-47c3-b5e8-c301b8d3e0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410126612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.410126612 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_sideload/latest


Test location /workspace/coverage/default/26.kmac_smoke.3412555805
Short name T449
Test name
Test status
Simulation time 9022753979 ps
CPU time 54.72 seconds
Started Feb 25 01:58:32 PM PST 24
Finished Feb 25 01:59:28 PM PST 24
Peak memory 226700 kb
Host smart-16abb95b-d942-4a3b-a64d-66b1af6a75c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412555805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.3412555805 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_smoke/latest


Test location /workspace/coverage/default/26.kmac_stress_all.3351423377
Short name T981
Test name
Test status
Simulation time 19326117232 ps
CPU time 1217.91 seconds
Started Feb 25 01:58:36 PM PST 24
Finished Feb 25 02:18:54 PM PST 24
Peak memory 373356 kb
Host smart-b183ac94-b353-44c4-aa6a-9fdc3dd815fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3351423377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.3351423377 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_stress_all/latest


Test location /workspace/coverage/default/26.kmac_test_vectors_kmac.1942052458
Short name T621
Test name
Test status
Simulation time 818642353 ps
CPU time 5.78 seconds
Started Feb 25 01:58:27 PM PST 24
Finished Feb 25 01:58:34 PM PST 24
Peak memory 219700 kb
Host smart-f0283f87-7035-44dc-8410-cdb63deb515c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942052458 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.kmac_test_vectors_kmac.1942052458 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/26.kmac_test_vectors_kmac_xof.3444647136
Short name T701
Test name
Test status
Simulation time 198305360 ps
CPU time 6.6 seconds
Started Feb 25 01:58:32 PM PST 24
Finished Feb 25 01:58:39 PM PST 24
Peak memory 218324 kb
Host smart-5bffbfa2-304b-473e-ab0b-285ec32ab1ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444647136 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.kmac_test_vectors_kmac_xof.3444647136 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_224.2885800839
Short name T598
Test name
Test status
Simulation time 274739972795 ps
CPU time 2281.73 seconds
Started Feb 25 01:58:32 PM PST 24
Finished Feb 25 02:36:34 PM PST 24
Peak memory 398508 kb
Host smart-5eee1e76-6070-4f47-86c0-c5c5ad8cb487
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2885800839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_224.2885800839 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_256.1337867506
Short name T596
Test name
Test status
Simulation time 78810577987 ps
CPU time 2019.14 seconds
Started Feb 25 01:58:32 PM PST 24
Finished Feb 25 02:32:12 PM PST 24
Peak memory 396584 kb
Host smart-e60d1bc3-0e42-4153-975d-c62cfd5c0b5c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1337867506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_256.1337867506 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_384.261873925
Short name T64
Test name
Test status
Simulation time 282078852309 ps
CPU time 1998.25 seconds
Started Feb 25 01:58:36 PM PST 24
Finished Feb 25 02:31:55 PM PST 24
Peak memory 341080 kb
Host smart-d1b8b881-2986-4087-a566-f0f96519fa7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=261873925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_384.261873925 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_512.3431553538
Short name T903
Test name
Test status
Simulation time 52053914319 ps
CPU time 1449.57 seconds
Started Feb 25 01:58:27 PM PST 24
Finished Feb 25 02:22:37 PM PST 24
Peak memory 304836 kb
Host smart-ac964bc0-eefa-49f5-b82b-d75e28f2bf6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3431553538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_512.3431553538 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/26.kmac_test_vectors_shake_128.1347340972
Short name T277
Test name
Test status
Simulation time 940411923648 ps
CPU time 6014.2 seconds
Started Feb 25 01:58:27 PM PST 24
Finished Feb 25 03:38:43 PM PST 24
Peak memory 655776 kb
Host smart-098c7a74-840c-4858-a519-b746ef80915b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1347340972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_128.1347340972 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/26.kmac_test_vectors_shake_256.3766546256
Short name T1017
Test name
Test status
Simulation time 128868893107 ps
CPU time 4367.09 seconds
Started Feb 25 01:58:31 PM PST 24
Finished Feb 25 03:11:19 PM PST 24
Peak memory 583812 kb
Host smart-4b9afe02-7bb8-4cef-aebb-431d31cfcb88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3766546256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_256.3766546256 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/27.kmac_alert_test.2128943083
Short name T1066
Test name
Test status
Simulation time 78790993 ps
CPU time 0.89 seconds
Started Feb 25 01:58:58 PM PST 24
Finished Feb 25 01:58:59 PM PST 24
Peak memory 218080 kb
Host smart-828d5249-1b00-495d-8f6f-a4101ab17fd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128943083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.2128943083 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_alert_test/latest


Test location /workspace/coverage/default/27.kmac_app.2461442501
Short name T834
Test name
Test status
Simulation time 3839860359 ps
CPU time 101.02 seconds
Started Feb 25 01:58:44 PM PST 24
Finished Feb 25 02:00:25 PM PST 24
Peak memory 234376 kb
Host smart-d7909215-9650-4535-ae11-480e68d81ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461442501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.2461442501 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_app/latest


Test location /workspace/coverage/default/27.kmac_burst_write.3584627173
Short name T467
Test name
Test status
Simulation time 156721070523 ps
CPU time 1493.29 seconds
Started Feb 25 01:58:35 PM PST 24
Finished Feb 25 02:23:29 PM PST 24
Peak memory 243044 kb
Host smart-4d2d6497-49ff-4270-9d74-ac0dfdcec273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584627173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.3584627173 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_burst_write/latest


Test location /workspace/coverage/default/27.kmac_entropy_refresh.1730121845
Short name T76
Test name
Test status
Simulation time 13742750947 ps
CPU time 303.77 seconds
Started Feb 25 01:58:46 PM PST 24
Finished Feb 25 02:03:50 PM PST 24
Peak memory 250244 kb
Host smart-7620fe43-9b90-4d70-86be-f10c42feb794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730121845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.1730121845 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/27.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/27.kmac_error.1049627915
Short name T613
Test name
Test status
Simulation time 22024109369 ps
CPU time 351.97 seconds
Started Feb 25 01:58:59 PM PST 24
Finished Feb 25 02:04:51 PM PST 24
Peak memory 273980 kb
Host smart-8c483d1b-5caf-47de-a9fd-72d2929e38a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049627915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.1049627915 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_error/latest


Test location /workspace/coverage/default/27.kmac_key_error.1389182200
Short name T522
Test name
Test status
Simulation time 1463058614 ps
CPU time 2.71 seconds
Started Feb 25 01:58:57 PM PST 24
Finished Feb 25 01:58:59 PM PST 24
Peak memory 218308 kb
Host smart-75e3e0e7-5e8d-479d-bf47-4870867f3bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389182200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.1389182200 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_key_error/latest


Test location /workspace/coverage/default/27.kmac_lc_escalation.2892879328
Short name T14
Test name
Test status
Simulation time 42246342 ps
CPU time 1.48 seconds
Started Feb 25 01:58:58 PM PST 24
Finished Feb 25 01:58:59 PM PST 24
Peak memory 218392 kb
Host smart-cbf56e90-030b-4f1d-bd44-be59325c114f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892879328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.2892879328 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/27.kmac_lc_escalation/latest


Test location /workspace/coverage/default/27.kmac_long_msg_and_output.3918171495
Short name T335
Test name
Test status
Simulation time 56357988231 ps
CPU time 1507.04 seconds
Started Feb 25 01:58:41 PM PST 24
Finished Feb 25 02:23:48 PM PST 24
Peak memory 345644 kb
Host smart-fb6e001e-d060-4048-8db5-34669d06c5e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918171495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_a
nd_output.3918171495 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/27.kmac_sideload.4077815516
Short name T610
Test name
Test status
Simulation time 7570638644 ps
CPU time 181.53 seconds
Started Feb 25 01:58:39 PM PST 24
Finished Feb 25 02:01:41 PM PST 24
Peak memory 239668 kb
Host smart-a5b810b2-a862-4fef-893b-83a37efb6c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077815516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.4077815516 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_sideload/latest


Test location /workspace/coverage/default/27.kmac_smoke.3531511957
Short name T304
Test name
Test status
Simulation time 7132198935 ps
CPU time 68.4 seconds
Started Feb 25 01:58:35 PM PST 24
Finished Feb 25 01:59:44 PM PST 24
Peak memory 224024 kb
Host smart-3684578f-9eea-4026-9d42-af9f3ac38b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531511957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.3531511957 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_smoke/latest


Test location /workspace/coverage/default/27.kmac_stress_all_with_rand_reset.2567170756
Short name T57
Test name
Test status
Simulation time 107731343241 ps
CPU time 823.21 seconds
Started Feb 25 01:58:57 PM PST 24
Finished Feb 25 02:12:40 PM PST 24
Peak memory 301052 kb
Host smart-33ebf99f-f4d7-4eb3-8176-605090942ae8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2567170756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all_with_rand_reset.2567170756 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/27.kmac_test_vectors_kmac.541104971
Short name T897
Test name
Test status
Simulation time 97544813 ps
CPU time 5.58 seconds
Started Feb 25 01:58:44 PM PST 24
Finished Feb 25 01:58:49 PM PST 24
Peak memory 219716 kb
Host smart-65dafc0c-a109-49e5-964e-0af2bdb5fccc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541104971 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.kmac_test_vectors_kmac.541104971 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/27.kmac_test_vectors_kmac_xof.2993030703
Short name T915
Test name
Test status
Simulation time 442663570 ps
CPU time 5.78 seconds
Started Feb 25 01:58:49 PM PST 24
Finished Feb 25 01:58:54 PM PST 24
Peak memory 218436 kb
Host smart-1c58c440-9a2d-4b2e-b4ac-d0137037815e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993030703 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.kmac_test_vectors_kmac_xof.2993030703 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_224.1419880386
Short name T729
Test name
Test status
Simulation time 181466610197 ps
CPU time 2156.62 seconds
Started Feb 25 01:58:40 PM PST 24
Finished Feb 25 02:34:37 PM PST 24
Peak memory 403124 kb
Host smart-fc9006a8-fe06-4d71-8bf9-97db6481ef56
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1419880386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_224.1419880386 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_256.3882889359
Short name T634
Test name
Test status
Simulation time 186049584284 ps
CPU time 2385.44 seconds
Started Feb 25 01:58:45 PM PST 24
Finished Feb 25 02:38:31 PM PST 24
Peak memory 385472 kb
Host smart-a7e6755f-6ac4-416f-a69d-8ad67e8e2df6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3882889359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_256.3882889359 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_384.1373029923
Short name T896
Test name
Test status
Simulation time 17317659978 ps
CPU time 1608.07 seconds
Started Feb 25 01:58:45 PM PST 24
Finished Feb 25 02:25:33 PM PST 24
Peak memory 338340 kb
Host smart-c74e36f5-b82a-4622-a735-72699488be42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1373029923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_384.1373029923 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_512.1613651521
Short name T526
Test name
Test status
Simulation time 45140256937 ps
CPU time 1421.61 seconds
Started Feb 25 01:58:48 PM PST 24
Finished Feb 25 02:22:30 PM PST 24
Peak memory 307472 kb
Host smart-1a73a012-dee5-46fc-8e1f-d065a2fdb16b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1613651521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_512.1613651521 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/27.kmac_test_vectors_shake_128.2108346795
Short name T588
Test name
Test status
Simulation time 865730471573 ps
CPU time 6202.19 seconds
Started Feb 25 01:58:46 PM PST 24
Finished Feb 25 03:42:09 PM PST 24
Peak memory 682728 kb
Host smart-7cb0cc63-00bc-4c49-8b3c-271ca0ff7f46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2108346795 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_128.2108346795 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/27.kmac_test_vectors_shake_256.1164615247
Short name T671
Test name
Test status
Simulation time 584203760353 ps
CPU time 5465.93 seconds
Started Feb 25 01:58:47 PM PST 24
Finished Feb 25 03:29:54 PM PST 24
Peak memory 561192 kb
Host smart-172ed866-e464-4a91-ad11-d7fe1e402b30
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1164615247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_256.1164615247 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/28.kmac_alert_test.1673903432
Short name T874
Test name
Test status
Simulation time 20230746 ps
CPU time 0.81 seconds
Started Feb 25 01:59:13 PM PST 24
Finished Feb 25 01:59:14 PM PST 24
Peak memory 219324 kb
Host smart-131adb70-bff6-4a42-a416-4175c1e155ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673903432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.1673903432 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_alert_test/latest


Test location /workspace/coverage/default/28.kmac_app.1289429027
Short name T808
Test name
Test status
Simulation time 1550020484 ps
CPU time 11.59 seconds
Started Feb 25 01:59:03 PM PST 24
Finished Feb 25 01:59:14 PM PST 24
Peak memory 219920 kb
Host smart-35f3847a-5f2d-4ad7-8c3a-cfc5853d33c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289429027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.1289429027 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_app/latest


Test location /workspace/coverage/default/28.kmac_burst_write.1307387745
Short name T662
Test name
Test status
Simulation time 32501069050 ps
CPU time 317.04 seconds
Started Feb 25 01:58:58 PM PST 24
Finished Feb 25 02:04:15 PM PST 24
Peak memory 241340 kb
Host smart-6bfc6255-0561-4cd1-a832-a540c7f7e1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307387745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.1307387745 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_burst_write/latest


Test location /workspace/coverage/default/28.kmac_error.1744071461
Short name T572
Test name
Test status
Simulation time 1529131692 ps
CPU time 126.67 seconds
Started Feb 25 01:59:04 PM PST 24
Finished Feb 25 02:01:11 PM PST 24
Peak memory 259352 kb
Host smart-4991e9c5-5a67-4b3a-a923-70d360dcedbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744071461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.1744071461 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_error/latest


Test location /workspace/coverage/default/28.kmac_key_error.582784319
Short name T38
Test name
Test status
Simulation time 1637898195 ps
CPU time 5.36 seconds
Started Feb 25 01:59:03 PM PST 24
Finished Feb 25 01:59:08 PM PST 24
Peak memory 218260 kb
Host smart-87f3674e-4f0f-42c9-8561-9625af634c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582784319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.582784319 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_key_error/latest


Test location /workspace/coverage/default/28.kmac_lc_escalation.3225288272
Short name T1071
Test name
Test status
Simulation time 27584528 ps
CPU time 1.16 seconds
Started Feb 25 01:59:03 PM PST 24
Finished Feb 25 01:59:04 PM PST 24
Peak memory 218340 kb
Host smart-771311b1-c03a-46e6-b448-1950fb911897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225288272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.3225288272 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/28.kmac_lc_escalation/latest


Test location /workspace/coverage/default/28.kmac_long_msg_and_output.2809254770
Short name T301
Test name
Test status
Simulation time 83391743522 ps
CPU time 943.37 seconds
Started Feb 25 01:58:57 PM PST 24
Finished Feb 25 02:14:41 PM PST 24
Peak memory 297712 kb
Host smart-52df87ee-ffd1-4f00-81ac-32fccdd31c74
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809254770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_a
nd_output.2809254770 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/28.kmac_sideload.1663769786
Short name T209
Test name
Test status
Simulation time 84870251423 ps
CPU time 571.72 seconds
Started Feb 25 01:58:57 PM PST 24
Finished Feb 25 02:08:29 PM PST 24
Peak memory 255500 kb
Host smart-8d1ff677-3300-4b11-b9c4-eb3f9c3bd650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663769786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.1663769786 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_sideload/latest


Test location /workspace/coverage/default/28.kmac_smoke.16913246
Short name T69
Test name
Test status
Simulation time 7138653585 ps
CPU time 34.22 seconds
Started Feb 25 01:58:58 PM PST 24
Finished Feb 25 01:59:33 PM PST 24
Peak memory 226544 kb
Host smart-458080fe-e663-4821-9b6b-f12ad69a96ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16913246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.16913246 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_smoke/latest


Test location /workspace/coverage/default/28.kmac_test_vectors_kmac.1230153292
Short name T350
Test name
Test status
Simulation time 133852845 ps
CPU time 5.88 seconds
Started Feb 25 01:59:03 PM PST 24
Finished Feb 25 01:59:09 PM PST 24
Peak memory 219824 kb
Host smart-88d1d47d-e55d-40a8-9f59-f5bb396b1767
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230153292 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.kmac_test_vectors_kmac.1230153292 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/28.kmac_test_vectors_kmac_xof.1864171395
Short name T982
Test name
Test status
Simulation time 166403953 ps
CPU time 5.63 seconds
Started Feb 25 01:59:03 PM PST 24
Finished Feb 25 01:59:08 PM PST 24
Peak memory 219768 kb
Host smart-34b5511e-44dd-4f8e-934e-80c3843380a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864171395 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.kmac_test_vectors_kmac_xof.1864171395 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_224.4013550792
Short name T211
Test name
Test status
Simulation time 401753843142 ps
CPU time 2495.6 seconds
Started Feb 25 01:58:57 PM PST 24
Finished Feb 25 02:40:33 PM PST 24
Peak memory 396296 kb
Host smart-aa6df4bd-9d25-4b6e-a36e-3aee9b9c9b23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4013550792 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_224.4013550792 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_256.3658371242
Short name T1067
Test name
Test status
Simulation time 40158962762 ps
CPU time 2191.98 seconds
Started Feb 25 01:58:58 PM PST 24
Finished Feb 25 02:35:30 PM PST 24
Peak memory 388944 kb
Host smart-adb6a618-cb08-4f91-921c-71b9bcffadac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3658371242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_256.3658371242 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_384.1142094686
Short name T942
Test name
Test status
Simulation time 101815770471 ps
CPU time 1918.24 seconds
Started Feb 25 01:58:59 PM PST 24
Finished Feb 25 02:30:57 PM PST 24
Peak memory 344208 kb
Host smart-e41ed769-1200-4585-ba26-df8f619c9ed5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1142094686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_384.1142094686 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_512.2880569895
Short name T619
Test name
Test status
Simulation time 546833869358 ps
CPU time 1283.06 seconds
Started Feb 25 01:58:58 PM PST 24
Finished Feb 25 02:20:21 PM PST 24
Peak memory 299568 kb
Host smart-08a6a06e-5fae-4ef4-bbc8-92f6c8ee99d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2880569895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_512.2880569895 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/28.kmac_test_vectors_shake_128.3347506628
Short name T883
Test name
Test status
Simulation time 1002958778888 ps
CPU time 5281.19 seconds
Started Feb 25 01:58:57 PM PST 24
Finished Feb 25 03:26:59 PM PST 24
Peak memory 659008 kb
Host smart-38de8831-76b8-4b24-86fd-5833baa82566
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3347506628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_128.3347506628 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/28.kmac_test_vectors_shake_256.1390458954
Short name T495
Test name
Test status
Simulation time 726782392091 ps
CPU time 5460.24 seconds
Started Feb 25 01:59:05 PM PST 24
Finished Feb 25 03:30:06 PM PST 24
Peak memory 592868 kb
Host smart-2583b536-47d2-439a-a920-9e6e5764f180
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1390458954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_256.1390458954 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/29.kmac_alert_test.1286920366
Short name T967
Test name
Test status
Simulation time 35811724 ps
CPU time 0.9 seconds
Started Feb 25 01:59:25 PM PST 24
Finished Feb 25 01:59:26 PM PST 24
Peak memory 219312 kb
Host smart-98aa0a44-64ea-4a51-bc81-94c4c67268c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286920366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.1286920366 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_alert_test/latest


Test location /workspace/coverage/default/29.kmac_app.1506264412
Short name T450
Test name
Test status
Simulation time 787900134 ps
CPU time 10.71 seconds
Started Feb 25 01:59:14 PM PST 24
Finished Feb 25 01:59:25 PM PST 24
Peak memory 224956 kb
Host smart-56bfa76b-a92e-4c3c-8187-7983e3b7322e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506264412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.1506264412 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_app/latest


Test location /workspace/coverage/default/29.kmac_burst_write.695487518
Short name T532
Test name
Test status
Simulation time 17674295351 ps
CPU time 932.17 seconds
Started Feb 25 01:59:15 PM PST 24
Finished Feb 25 02:14:47 PM PST 24
Peak memory 236660 kb
Host smart-bc55c344-bc8e-4a9b-880c-08bfdaea3d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695487518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.695487518 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_burst_write/latest


Test location /workspace/coverage/default/29.kmac_entropy_refresh.859709283
Short name T689
Test name
Test status
Simulation time 3705845141 ps
CPU time 91.76 seconds
Started Feb 25 01:59:14 PM PST 24
Finished Feb 25 02:00:46 PM PST 24
Peak memory 231888 kb
Host smart-50be03f6-0fdf-4513-a2bf-50fab94760a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859709283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.859709283 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/29.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/29.kmac_error.2796158255
Short name T400
Test name
Test status
Simulation time 32971395058 ps
CPU time 253.6 seconds
Started Feb 25 01:59:12 PM PST 24
Finished Feb 25 02:03:26 PM PST 24
Peak memory 259484 kb
Host smart-5bcf8f9a-7589-4082-9783-ff862ac19b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796158255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.2796158255 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_error/latest


Test location /workspace/coverage/default/29.kmac_key_error.3614083662
Short name T773
Test name
Test status
Simulation time 69883038 ps
CPU time 1.28 seconds
Started Feb 25 01:59:13 PM PST 24
Finished Feb 25 01:59:14 PM PST 24
Peak memory 218296 kb
Host smart-5500c9f8-c220-489c-b4fe-01c97ab51805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614083662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.3614083662 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_key_error/latest


Test location /workspace/coverage/default/29.kmac_lc_escalation.223926541
Short name T61
Test name
Test status
Simulation time 89983112 ps
CPU time 1.24 seconds
Started Feb 25 01:59:18 PM PST 24
Finished Feb 25 01:59:20 PM PST 24
Peak memory 219436 kb
Host smart-b09ebf16-3265-4932-b41b-1638b8a789f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223926541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.223926541 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/29.kmac_lc_escalation/latest


Test location /workspace/coverage/default/29.kmac_long_msg_and_output.3677689169
Short name T329
Test name
Test status
Simulation time 1904357766 ps
CPU time 37.76 seconds
Started Feb 25 01:59:14 PM PST 24
Finished Feb 25 01:59:52 PM PST 24
Peak memory 227156 kb
Host smart-52298e48-0ff5-4943-87dd-3343ac7dcdda
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677689169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_a
nd_output.3677689169 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/29.kmac_sideload.2397777073
Short name T886
Test name
Test status
Simulation time 7780716148 ps
CPU time 297.51 seconds
Started Feb 25 01:59:13 PM PST 24
Finished Feb 25 02:04:10 PM PST 24
Peak memory 244064 kb
Host smart-33ca8ff9-51cb-4097-aa86-2ae3eb98c865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397777073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.2397777073 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_sideload/latest


Test location /workspace/coverage/default/29.kmac_smoke.3908996405
Short name T243
Test name
Test status
Simulation time 36835796838 ps
CPU time 58.17 seconds
Started Feb 25 01:59:16 PM PST 24
Finished Feb 25 02:00:15 PM PST 24
Peak memory 225216 kb
Host smart-ea1ab49c-bc59-498b-ad06-16800bdf2ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908996405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.3908996405 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_smoke/latest


Test location /workspace/coverage/default/29.kmac_stress_all.2115715065
Short name T173
Test name
Test status
Simulation time 67034949150 ps
CPU time 866.31 seconds
Started Feb 25 01:59:12 PM PST 24
Finished Feb 25 02:13:39 PM PST 24
Peak memory 313244 kb
Host smart-41539303-3ee3-4b77-a987-f7dc3b8edc74
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2115715065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.2115715065 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_stress_all/latest


Test location /workspace/coverage/default/29.kmac_test_vectors_kmac.2515096531
Short name T993
Test name
Test status
Simulation time 114371765 ps
CPU time 6.48 seconds
Started Feb 25 01:59:15 PM PST 24
Finished Feb 25 01:59:22 PM PST 24
Peak memory 219868 kb
Host smart-1183197b-873e-4361-9731-44202cee8d6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515096531 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.kmac_test_vectors_kmac.2515096531 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/29.kmac_test_vectors_kmac_xof.781733605
Short name T754
Test name
Test status
Simulation time 396355908 ps
CPU time 6.55 seconds
Started Feb 25 01:59:15 PM PST 24
Finished Feb 25 01:59:22 PM PST 24
Peak memory 218372 kb
Host smart-267d022a-bd15-461f-a2d0-daa6d8ded09c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781733605 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.kmac_test_vectors_kmac_xof.781733605 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_224.2080015418
Short name T581
Test name
Test status
Simulation time 96140483487 ps
CPU time 2033.4 seconds
Started Feb 25 01:59:16 PM PST 24
Finished Feb 25 02:33:10 PM PST 24
Peak memory 395164 kb
Host smart-522e1db6-2dd7-4e6b-ba70-97ca0ff026e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2080015418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_224.2080015418 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_256.3523490901
Short name T842
Test name
Test status
Simulation time 93341088085 ps
CPU time 2370.23 seconds
Started Feb 25 01:59:14 PM PST 24
Finished Feb 25 02:38:45 PM PST 24
Peak memory 388748 kb
Host smart-7503549c-f9f7-4bce-ad11-178d7be4e28a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3523490901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_256.3523490901 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_384.189864176
Short name T3
Test name
Test status
Simulation time 48992923172 ps
CPU time 1748.18 seconds
Started Feb 25 01:59:14 PM PST 24
Finished Feb 25 02:28:23 PM PST 24
Peak memory 343272 kb
Host smart-20a0d6fa-e5e3-41d3-98e0-e8322e31b842
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=189864176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_384.189864176 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_512.4278402515
Short name T448
Test name
Test status
Simulation time 12897247773 ps
CPU time 1216.88 seconds
Started Feb 25 01:59:14 PM PST 24
Finished Feb 25 02:19:32 PM PST 24
Peak memory 298232 kb
Host smart-ca22abb8-e329-4fdc-9e00-2dd1ba89ea44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4278402515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_512.4278402515 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/29.kmac_test_vectors_shake_128.774759105
Short name T513
Test name
Test status
Simulation time 873878902665 ps
CPU time 6070.26 seconds
Started Feb 25 01:59:14 PM PST 24
Finished Feb 25 03:40:26 PM PST 24
Peak memory 659320 kb
Host smart-2208527c-1a51-448b-aa2d-899cedb18b78
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=774759105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_128.774759105 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/29.kmac_test_vectors_shake_256.2065486816
Short name T595
Test name
Test status
Simulation time 57237318981 ps
CPU time 4652.44 seconds
Started Feb 25 01:59:13 PM PST 24
Finished Feb 25 03:16:46 PM PST 24
Peak memory 575800 kb
Host smart-e5f91131-98e7-4c05-b8df-3b9b3f8b61cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2065486816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_256.2065486816 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/3.kmac_alert_test.1115755749
Short name T253
Test name
Test status
Simulation time 31697326 ps
CPU time 0.79 seconds
Started Feb 25 01:55:43 PM PST 24
Finished Feb 25 01:55:44 PM PST 24
Peak memory 219308 kb
Host smart-73b42024-ff84-4393-9078-198e79ff2016
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115755749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.1115755749 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_alert_test/latest


Test location /workspace/coverage/default/3.kmac_app.2157596086
Short name T235
Test name
Test status
Simulation time 12829829184 ps
CPU time 138.57 seconds
Started Feb 25 01:55:30 PM PST 24
Finished Feb 25 01:57:49 PM PST 24
Peak memory 237960 kb
Host smart-379e6903-5098-430b-a7d7-2fa22464aa7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157596086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.2157596086 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_app/latest


Test location /workspace/coverage/default/3.kmac_app_with_partial_data.400591066
Short name T632
Test name
Test status
Simulation time 8485656741 ps
CPU time 356 seconds
Started Feb 25 01:55:31 PM PST 24
Finished Feb 25 02:01:27 PM PST 24
Peak memory 250888 kb
Host smart-2160571c-141d-4b83-b550-a30e3df867b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400591066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.400591066 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/3.kmac_app_with_partial_data/latest


Test location /workspace/coverage/default/3.kmac_burst_write.322142760
Short name T990
Test name
Test status
Simulation time 56436480452 ps
CPU time 1629.76 seconds
Started Feb 25 01:55:33 PM PST 24
Finished Feb 25 02:22:44 PM PST 24
Peak memory 241700 kb
Host smart-ab348735-5af7-4d0f-ba35-4f0e184497bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322142760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.322142760 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_burst_write/latest


Test location /workspace/coverage/default/3.kmac_edn_timeout_error.749984456
Short name T434
Test name
Test status
Simulation time 1982289182 ps
CPU time 52.66 seconds
Started Feb 25 01:55:34 PM PST 24
Finished Feb 25 01:56:27 PM PST 24
Peak memory 236600 kb
Host smart-1404e13f-28db-4867-a292-bca2257ced13
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=749984456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.749984456 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/3.kmac_entropy_mode_error.873763033
Short name T537
Test name
Test status
Simulation time 19040010 ps
CPU time 0.98 seconds
Started Feb 25 01:55:33 PM PST 24
Finished Feb 25 01:55:34 PM PST 24
Peak memory 218104 kb
Host smart-541da509-bd62-40e9-bde9-54dab633caa8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=873763033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.873763033 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/3.kmac_entropy_ready_error.323200434
Short name T39
Test name
Test status
Simulation time 3622698075 ps
CPU time 60.51 seconds
Started Feb 25 01:55:42 PM PST 24
Finished Feb 25 01:56:43 PM PST 24
Peak memory 221740 kb
Host smart-617ff36c-f6de-48e9-90bf-d78e45c7291e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323200434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.323200434 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_ready_error/latest


Test location /workspace/coverage/default/3.kmac_entropy_refresh.3059321506
Short name T98
Test name
Test status
Simulation time 23597403149 ps
CPU time 172.25 seconds
Started Feb 25 01:55:31 PM PST 24
Finished Feb 25 01:58:23 PM PST 24
Peak memory 240536 kb
Host smart-995208fe-0b31-4f35-9645-d71e7394dac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059321506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.3059321506 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/3.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/3.kmac_error.1290450677
Short name T170
Test name
Test status
Simulation time 553308989 ps
CPU time 10.7 seconds
Started Feb 25 01:55:31 PM PST 24
Finished Feb 25 01:55:42 PM PST 24
Peak memory 226528 kb
Host smart-f00f7af4-6955-4a47-ba7c-9b96d617885d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290450677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.1290450677 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_error/latest


Test location /workspace/coverage/default/3.kmac_key_error.2630900945
Short name T104
Test name
Test status
Simulation time 795022848 ps
CPU time 4.49 seconds
Started Feb 25 01:55:33 PM PST 24
Finished Feb 25 01:55:39 PM PST 24
Peak memory 218300 kb
Host smart-e401b66a-1e7b-4657-b4f3-c9ad9ffc6ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630900945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.2630900945 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_key_error/latest


Test location /workspace/coverage/default/3.kmac_lc_escalation.1106535980
Short name T68
Test name
Test status
Simulation time 1142127082 ps
CPU time 49.13 seconds
Started Feb 25 01:55:40 PM PST 24
Finished Feb 25 01:56:30 PM PST 24
Peak memory 238116 kb
Host smart-3b8ab731-90b4-40c3-9d46-6c57adf9d68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106535980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.1106535980 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/3.kmac_lc_escalation/latest


Test location /workspace/coverage/default/3.kmac_long_msg_and_output.3795488699
Short name T333
Test name
Test status
Simulation time 208025527351 ps
CPU time 1422.43 seconds
Started Feb 25 01:55:31 PM PST 24
Finished Feb 25 02:19:14 PM PST 24
Peak memory 320848 kb
Host smart-f2e469cc-ae0d-41b4-ba80-5f2d59e821f1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795488699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_an
d_output.3795488699 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/3.kmac_mubi.1864266900
Short name T55
Test name
Test status
Simulation time 16470890194 ps
CPU time 389.71 seconds
Started Feb 25 01:55:30 PM PST 24
Finished Feb 25 02:02:00 PM PST 24
Peak memory 253368 kb
Host smart-c36df91b-a74a-4805-8671-cb69c664d56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864266900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.1864266900 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mubi/latest


Test location /workspace/coverage/default/3.kmac_sec_cm.3298862676
Short name T108
Test name
Test status
Simulation time 15023322953 ps
CPU time 58.5 seconds
Started Feb 25 01:55:42 PM PST 24
Finished Feb 25 01:56:41 PM PST 24
Peak memory 265584 kb
Host smart-5c18a610-27ec-4cb0-b760-438b3df1980c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298862676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.3298862676 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/3.kmac_sec_cm/latest


Test location /workspace/coverage/default/3.kmac_sideload.2319148292
Short name T389
Test name
Test status
Simulation time 49072494103 ps
CPU time 447.28 seconds
Started Feb 25 01:55:30 PM PST 24
Finished Feb 25 02:02:57 PM PST 24
Peak memory 252740 kb
Host smart-ccf468a3-a78d-46ee-8237-f52768cddf1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319148292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.2319148292 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_sideload/latest


Test location /workspace/coverage/default/3.kmac_smoke.4188880431
Short name T322
Test name
Test status
Simulation time 10868715749 ps
CPU time 44.15 seconds
Started Feb 25 01:55:29 PM PST 24
Finished Feb 25 01:56:13 PM PST 24
Peak memory 226568 kb
Host smart-9b9dc0c0-f17c-4af0-b96d-2733887a9038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188880431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.4188880431 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_smoke/latest


Test location /workspace/coverage/default/3.kmac_stress_all.3803178105
Short name T794
Test name
Test status
Simulation time 16685295051 ps
CPU time 1363.65 seconds
Started Feb 25 01:55:41 PM PST 24
Finished Feb 25 02:18:25 PM PST 24
Peak memory 358016 kb
Host smart-91ec4b36-5461-4abe-94fc-d8f5bf6ea80b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3803178105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.3803178105 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_stress_all/latest


Test location /workspace/coverage/default/3.kmac_test_vectors_kmac.2303296701
Short name T945
Test name
Test status
Simulation time 228777229 ps
CPU time 5.55 seconds
Started Feb 25 01:55:30 PM PST 24
Finished Feb 25 01:55:36 PM PST 24
Peak memory 218416 kb
Host smart-6d4321d4-107e-4c88-be7e-3bfaa71b0bc7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303296701 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.kmac_test_vectors_kmac.2303296701 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/3.kmac_test_vectors_kmac_xof.3213910995
Short name T223
Test name
Test status
Simulation time 203357628 ps
CPU time 6.84 seconds
Started Feb 25 01:55:33 PM PST 24
Finished Feb 25 01:55:39 PM PST 24
Peak memory 218464 kb
Host smart-31c400d7-2c9c-48ff-8e44-b38ea6b430c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213910995 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.kmac_test_vectors_kmac_xof.3213910995 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_224.2071157737
Short name T1050
Test name
Test status
Simulation time 691488713029 ps
CPU time 2782.96 seconds
Started Feb 25 01:55:30 PM PST 24
Finished Feb 25 02:41:53 PM PST 24
Peak memory 397920 kb
Host smart-81020a44-9ff1-4a30-8137-0708fba9b3e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2071157737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.2071157737 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_256.590209837
Short name T500
Test name
Test status
Simulation time 194784327547 ps
CPU time 2369.9 seconds
Started Feb 25 01:55:33 PM PST 24
Finished Feb 25 02:35:04 PM PST 24
Peak memory 394264 kb
Host smart-11c2fc28-5374-44c1-a0dd-dedc3a9e2c4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=590209837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.590209837 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_384.2892739868
Short name T524
Test name
Test status
Simulation time 244633863968 ps
CPU time 1819.14 seconds
Started Feb 25 01:55:29 PM PST 24
Finished Feb 25 02:25:48 PM PST 24
Peak memory 339732 kb
Host smart-2a8b13b1-0571-46c6-bfc8-7ab400f487ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2892739868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.2892739868 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_512.3597200265
Short name T746
Test name
Test status
Simulation time 99522777864 ps
CPU time 1528.38 seconds
Started Feb 25 01:55:32 PM PST 24
Finished Feb 25 02:21:01 PM PST 24
Peak memory 305836 kb
Host smart-47a26cba-1e6e-49cd-801a-ed6ce514ebcf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3597200265 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.3597200265 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/3.kmac_test_vectors_shake_128.1186906574
Short name T530
Test name
Test status
Simulation time 372517258447 ps
CPU time 6266.77 seconds
Started Feb 25 01:55:33 PM PST 24
Finished Feb 25 03:40:00 PM PST 24
Peak memory 657116 kb
Host smart-a0ac2459-d7bc-4348-bd9b-1820c4b1f830
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1186906574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.1186906574 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/3.kmac_test_vectors_shake_256.893434905
Short name T777
Test name
Test status
Simulation time 313528305210 ps
CPU time 5405.3 seconds
Started Feb 25 01:55:33 PM PST 24
Finished Feb 25 03:25:40 PM PST 24
Peak memory 585664 kb
Host smart-abda7562-23c4-4752-b76d-54c970baf5fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=893434905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.893434905 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/30.kmac_alert_test.2920871001
Short name T279
Test name
Test status
Simulation time 14169415 ps
CPU time 0.85 seconds
Started Feb 25 01:59:33 PM PST 24
Finished Feb 25 01:59:34 PM PST 24
Peak memory 218204 kb
Host smart-f6131c76-ecc8-4833-aa6e-c2e268b1c376
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920871001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.2920871001 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_alert_test/latest


Test location /workspace/coverage/default/30.kmac_app.611876488
Short name T866
Test name
Test status
Simulation time 5425054721 ps
CPU time 273.76 seconds
Started Feb 25 01:59:27 PM PST 24
Finished Feb 25 02:04:02 PM PST 24
Peak memory 248596 kb
Host smart-b340b158-5ef9-4d50-a60d-44eaa988f3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611876488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.611876488 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_app/latest


Test location /workspace/coverage/default/30.kmac_burst_write.4006281640
Short name T565
Test name
Test status
Simulation time 24595901146 ps
CPU time 943.53 seconds
Started Feb 25 01:59:25 PM PST 24
Finished Feb 25 02:15:09 PM PST 24
Peak memory 242952 kb
Host smart-69a011ed-1fe3-4bf7-9c0b-2faeeb0c5749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006281640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.4006281640 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_burst_write/latest


Test location /workspace/coverage/default/30.kmac_entropy_refresh.1751929543
Short name T789
Test name
Test status
Simulation time 5770029265 ps
CPU time 126.69 seconds
Started Feb 25 01:59:30 PM PST 24
Finished Feb 25 02:01:37 PM PST 24
Peak memory 236464 kb
Host smart-98fc08a7-832f-45b6-b2ea-52d832041b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751929543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.1751929543 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/30.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/30.kmac_key_error.1606010516
Short name T325
Test name
Test status
Simulation time 631049254 ps
CPU time 4.18 seconds
Started Feb 25 01:59:27 PM PST 24
Finished Feb 25 01:59:32 PM PST 24
Peak memory 218256 kb
Host smart-605d4a48-913f-4ef7-825e-81235779654b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606010516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.1606010516 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_key_error/latest


Test location /workspace/coverage/default/30.kmac_lc_escalation.4139127403
Short name T360
Test name
Test status
Simulation time 126921003 ps
CPU time 1.46 seconds
Started Feb 25 01:59:40 PM PST 24
Finished Feb 25 01:59:42 PM PST 24
Peak memory 219292 kb
Host smart-f18cdd1c-5733-49e8-b296-68e16aae55f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139127403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.4139127403 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/30.kmac_lc_escalation/latest


Test location /workspace/coverage/default/30.kmac_long_msg_and_output.835331417
Short name T703
Test name
Test status
Simulation time 174288345714 ps
CPU time 1204.98 seconds
Started Feb 25 01:59:26 PM PST 24
Finished Feb 25 02:19:31 PM PST 24
Peak memory 313180 kb
Host smart-ddb10f94-01b4-40fd-b377-ea4137ce922e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835331417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_an
d_output.835331417 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/30.kmac_sideload.2441387928
Short name T948
Test name
Test status
Simulation time 54555470719 ps
CPU time 200.03 seconds
Started Feb 25 01:59:27 PM PST 24
Finished Feb 25 02:02:47 PM PST 24
Peak memory 237372 kb
Host smart-b8b68d31-000d-44dd-8c1c-a20d94bd6017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441387928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.2441387928 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_sideload/latest


Test location /workspace/coverage/default/30.kmac_smoke.2981902952
Short name T973
Test name
Test status
Simulation time 2354243432 ps
CPU time 34.76 seconds
Started Feb 25 01:59:29 PM PST 24
Finished Feb 25 02:00:04 PM PST 24
Peak memory 226612 kb
Host smart-563a294e-574f-4ae4-a852-97fa8e864013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981902952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.2981902952 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_smoke/latest


Test location /workspace/coverage/default/30.kmac_stress_all.1413283777
Short name T844
Test name
Test status
Simulation time 9690592990 ps
CPU time 419.24 seconds
Started Feb 25 01:59:32 PM PST 24
Finished Feb 25 02:06:31 PM PST 24
Peak memory 289172 kb
Host smart-58d496bf-bf84-4759-aa8f-3eb3e67ad6a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1413283777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.1413283777 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_stress_all/latest


Test location /workspace/coverage/default/30.kmac_test_vectors_kmac.1093006751
Short name T488
Test name
Test status
Simulation time 437001551 ps
CPU time 7.95 seconds
Started Feb 25 01:59:27 PM PST 24
Finished Feb 25 01:59:35 PM PST 24
Peak memory 218452 kb
Host smart-7c80777f-1963-445a-a21c-df0f30fb8dfb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093006751 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.kmac_test_vectors_kmac.1093006751 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/30.kmac_test_vectors_kmac_xof.784390036
Short name T354
Test name
Test status
Simulation time 836698145 ps
CPU time 6.24 seconds
Started Feb 25 01:59:29 PM PST 24
Finished Feb 25 01:59:35 PM PST 24
Peak memory 219788 kb
Host smart-1be4c55a-b577-4143-8fc1-28f46bd80555
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784390036 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.kmac_test_vectors_kmac_xof.784390036 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_224.3347162533
Short name T398
Test name
Test status
Simulation time 293316116168 ps
CPU time 2177.94 seconds
Started Feb 25 01:59:29 PM PST 24
Finished Feb 25 02:35:48 PM PST 24
Peak memory 404820 kb
Host smart-a4614fd6-10a4-45ff-8ff5-9bf5e46173f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3347162533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_224.3347162533 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_256.4008759859
Short name T625
Test name
Test status
Simulation time 115311198717 ps
CPU time 2131.84 seconds
Started Feb 25 01:59:27 PM PST 24
Finished Feb 25 02:35:00 PM PST 24
Peak memory 392552 kb
Host smart-4f31b0b4-ade6-4042-bcce-b34abb9c894d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4008759859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_256.4008759859 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_384.4285169685
Short name T820
Test name
Test status
Simulation time 260385594910 ps
CPU time 1792.3 seconds
Started Feb 25 01:59:26 PM PST 24
Finished Feb 25 02:29:18 PM PST 24
Peak memory 339920 kb
Host smart-c6fa0afd-d6c1-4bff-96ce-47963e857937
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4285169685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_384.4285169685 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_512.4052021869
Short name T162
Test name
Test status
Simulation time 21074292459 ps
CPU time 1157.66 seconds
Started Feb 25 01:59:29 PM PST 24
Finished Feb 25 02:18:47 PM PST 24
Peak memory 301172 kb
Host smart-a4435bca-fa53-47a2-a5c5-969012a61c61
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4052021869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_512.4052021869 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/30.kmac_test_vectors_shake_128.115886148
Short name T750
Test name
Test status
Simulation time 250414293737 ps
CPU time 5268.46 seconds
Started Feb 25 01:59:26 PM PST 24
Finished Feb 25 03:27:16 PM PST 24
Peak memory 655468 kb
Host smart-4c6a8576-ba4f-4486-bce1-48a30326d7d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=115886148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_128.115886148 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/31.kmac_alert_test.143185632
Short name T352
Test name
Test status
Simulation time 201882075 ps
CPU time 0.87 seconds
Started Feb 25 01:59:50 PM PST 24
Finished Feb 25 01:59:51 PM PST 24
Peak memory 219320 kb
Host smart-6d64603e-be9a-4c26-a0df-f98be87a3d70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143185632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.143185632 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/31.kmac_alert_test/latest


Test location /workspace/coverage/default/31.kmac_app.4279661781
Short name T541
Test name
Test status
Simulation time 6364027362 ps
CPU time 159.82 seconds
Started Feb 25 01:59:46 PM PST 24
Finished Feb 25 02:02:27 PM PST 24
Peak memory 239752 kb
Host smart-b97c4622-c268-40dc-9ae4-c95efe2e44e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279661781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.4279661781 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_app/latest


Test location /workspace/coverage/default/31.kmac_burst_write.252323785
Short name T149
Test name
Test status
Simulation time 8161770381 ps
CPU time 303.92 seconds
Started Feb 25 01:59:46 PM PST 24
Finished Feb 25 02:04:50 PM PST 24
Peak memory 239116 kb
Host smart-0e6c8f2a-0761-4199-b35f-40865251ed8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252323785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.252323785 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_burst_write/latest


Test location /workspace/coverage/default/31.kmac_entropy_refresh.1570649682
Short name T988
Test name
Test status
Simulation time 8152769559 ps
CPU time 246.12 seconds
Started Feb 25 01:59:48 PM PST 24
Finished Feb 25 02:03:55 PM PST 24
Peak memory 245184 kb
Host smart-a97e6139-3f91-4f2b-a39b-7c729591a6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570649682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.1570649682 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/31.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/31.kmac_error.267633106
Short name T828
Test name
Test status
Simulation time 21000343063 ps
CPU time 268.17 seconds
Started Feb 25 01:59:49 PM PST 24
Finished Feb 25 02:04:18 PM PST 24
Peak memory 259412 kb
Host smart-8f3471bc-1963-4a27-bbd9-bc7f57f32b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267633106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.267633106 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_error/latest


Test location /workspace/coverage/default/31.kmac_key_error.2538614640
Short name T989
Test name
Test status
Simulation time 1237940354 ps
CPU time 6.49 seconds
Started Feb 25 01:59:46 PM PST 24
Finished Feb 25 01:59:53 PM PST 24
Peak memory 218348 kb
Host smart-efc3534d-4493-4bea-93d0-52992214073e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538614640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.2538614640 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_key_error/latest


Test location /workspace/coverage/default/31.kmac_long_msg_and_output.225436942
Short name T741
Test name
Test status
Simulation time 97527347666 ps
CPU time 2680.15 seconds
Started Feb 25 01:59:33 PM PST 24
Finished Feb 25 02:44:13 PM PST 24
Peak memory 441432 kb
Host smart-a1fda013-3111-402a-866f-26373bd5e696
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225436942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_an
d_output.225436942 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/31.kmac_sideload.4092568898
Short name T968
Test name
Test status
Simulation time 4924750254 ps
CPU time 432.88 seconds
Started Feb 25 01:59:34 PM PST 24
Finished Feb 25 02:06:47 PM PST 24
Peak memory 255376 kb
Host smart-6b696a15-3a9e-4ee3-ba7e-779977182cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092568898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.4092568898 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_sideload/latest


Test location /workspace/coverage/default/31.kmac_smoke.1459881193
Short name T515
Test name
Test status
Simulation time 484906248 ps
CPU time 13.37 seconds
Started Feb 25 01:59:34 PM PST 24
Finished Feb 25 01:59:47 PM PST 24
Peak memory 226592 kb
Host smart-81a39990-d0d3-4f8e-a408-65c9083dfd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459881193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.1459881193 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_smoke/latest


Test location /workspace/coverage/default/31.kmac_stress_all.222609523
Short name T616
Test name
Test status
Simulation time 40589532564 ps
CPU time 1536.3 seconds
Started Feb 25 01:59:47 PM PST 24
Finished Feb 25 02:25:24 PM PST 24
Peak memory 381556 kb
Host smart-3a98a141-94ca-4924-93fe-fc8987c845ef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=222609523 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.222609523 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_stress_all/latest


Test location /workspace/coverage/default/31.kmac_test_vectors_kmac.2684632394
Short name T268
Test name
Test status
Simulation time 218737819 ps
CPU time 6.39 seconds
Started Feb 25 01:59:46 PM PST 24
Finished Feb 25 01:59:53 PM PST 24
Peak memory 219776 kb
Host smart-90d70214-bb8b-422c-83b2-b9037ff97384
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684632394 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.kmac_test_vectors_kmac.2684632394 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/31.kmac_test_vectors_kmac_xof.3328650247
Short name T972
Test name
Test status
Simulation time 121988041 ps
CPU time 5.87 seconds
Started Feb 25 01:59:47 PM PST 24
Finished Feb 25 01:59:53 PM PST 24
Peak memory 219748 kb
Host smart-47254ac0-e581-40ee-a53a-b488d95f3a28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328650247 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.kmac_test_vectors_kmac_xof.3328650247 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_224.3209390966
Short name T109
Test name
Test status
Simulation time 316676308084 ps
CPU time 2531.47 seconds
Started Feb 25 01:59:33 PM PST 24
Finished Feb 25 02:41:45 PM PST 24
Peak memory 405032 kb
Host smart-23959707-5ef3-458b-9b44-c05e03469a33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3209390966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_224.3209390966 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_256.3706750806
Short name T296
Test name
Test status
Simulation time 78991353728 ps
CPU time 2240.39 seconds
Started Feb 25 01:59:36 PM PST 24
Finished Feb 25 02:36:57 PM PST 24
Peak memory 384784 kb
Host smart-cb4e4922-771e-4ecc-8233-d1d9313fd736
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3706750806 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_256.3706750806 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_384.1282978167
Short name T862
Test name
Test status
Simulation time 57015369180 ps
CPU time 1790.62 seconds
Started Feb 25 01:59:36 PM PST 24
Finished Feb 25 02:29:27 PM PST 24
Peak memory 339736 kb
Host smart-bee8fd03-1948-4f29-99be-0434e2174321
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1282978167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_384.1282978167 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_512.2111279371
Short name T416
Test name
Test status
Simulation time 34001481800 ps
CPU time 1369.44 seconds
Started Feb 25 01:59:50 PM PST 24
Finished Feb 25 02:22:40 PM PST 24
Peak memory 302384 kb
Host smart-282e55b4-6955-4750-9d34-ba808b17b3b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2111279371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_512.2111279371 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/31.kmac_test_vectors_shake_128.3691980900
Short name T956
Test name
Test status
Simulation time 282667623807 ps
CPU time 5276.21 seconds
Started Feb 25 01:59:46 PM PST 24
Finished Feb 25 03:27:43 PM PST 24
Peak memory 649316 kb
Host smart-3ee5ef4c-280b-4caf-a5f6-a99f86e8b57a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3691980900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_128.3691980900 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/31.kmac_test_vectors_shake_256.1103290980
Short name T234
Test name
Test status
Simulation time 52322491168 ps
CPU time 4524 seconds
Started Feb 25 01:59:51 PM PST 24
Finished Feb 25 03:15:16 PM PST 24
Peak memory 556508 kb
Host smart-f20f240d-2120-4e7c-88f0-ba216dd41168
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1103290980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_256.1103290980 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/32.kmac_alert_test.2769223453
Short name T650
Test name
Test status
Simulation time 79851191 ps
CPU time 0.92 seconds
Started Feb 25 02:00:10 PM PST 24
Finished Feb 25 02:00:11 PM PST 24
Peak memory 218116 kb
Host smart-b0cc910d-df3a-47e0-9bf3-d40e3fc13330
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769223453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.2769223453 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_alert_test/latest


Test location /workspace/coverage/default/32.kmac_app.3930634466
Short name T931
Test name
Test status
Simulation time 7074373920 ps
CPU time 57.53 seconds
Started Feb 25 01:59:59 PM PST 24
Finished Feb 25 02:00:56 PM PST 24
Peak memory 229764 kb
Host smart-bd54d5b5-8166-421e-8b67-0d375effb972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930634466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.3930634466 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_app/latest


Test location /workspace/coverage/default/32.kmac_burst_write.619938805
Short name T33
Test name
Test status
Simulation time 8513108891 ps
CPU time 950.01 seconds
Started Feb 25 01:59:51 PM PST 24
Finished Feb 25 02:15:42 PM PST 24
Peak memory 236620 kb
Host smart-7005b1a7-d029-449a-a602-fd4339475a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619938805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.619938805 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_burst_write/latest


Test location /workspace/coverage/default/32.kmac_entropy_refresh.1360134852
Short name T499
Test name
Test status
Simulation time 23819182173 ps
CPU time 74.99 seconds
Started Feb 25 02:00:07 PM PST 24
Finished Feb 25 02:01:23 PM PST 24
Peak memory 231992 kb
Host smart-b87f0ea8-bc5f-44b8-9c1d-3ea0efe9b39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360134852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.1360134852 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/32.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/32.kmac_error.1065875137
Short name T654
Test name
Test status
Simulation time 1724939574 ps
CPU time 131.44 seconds
Started Feb 25 02:00:07 PM PST 24
Finished Feb 25 02:02:18 PM PST 24
Peak memory 242964 kb
Host smart-826a0432-3328-47c5-bab8-4cbe27449218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065875137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.1065875137 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_error/latest


Test location /workspace/coverage/default/32.kmac_key_error.3926985027
Short name T430
Test name
Test status
Simulation time 497717016 ps
CPU time 3.68 seconds
Started Feb 25 01:59:59 PM PST 24
Finished Feb 25 02:00:03 PM PST 24
Peak memory 218340 kb
Host smart-f83dbec0-c0f5-4c3a-bda8-5fa2020ab8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926985027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.3926985027 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_key_error/latest


Test location /workspace/coverage/default/32.kmac_lc_escalation.922252133
Short name T924
Test name
Test status
Simulation time 38689059 ps
CPU time 1.34 seconds
Started Feb 25 01:59:59 PM PST 24
Finished Feb 25 02:00:00 PM PST 24
Peak memory 219176 kb
Host smart-c4582a4b-e5cf-421b-a5d7-43c08cf7bfc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922252133 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.922252133 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/32.kmac_lc_escalation/latest


Test location /workspace/coverage/default/32.kmac_long_msg_and_output.2748310734
Short name T939
Test name
Test status
Simulation time 60158302517 ps
CPU time 1743.26 seconds
Started Feb 25 01:59:49 PM PST 24
Finished Feb 25 02:28:53 PM PST 24
Peak memory 355532 kb
Host smart-f69881bd-f3d2-49d4-98a2-e636f98c1119
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748310734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_a
nd_output.2748310734 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/32.kmac_sideload.2468665655
Short name T568
Test name
Test status
Simulation time 21405206964 ps
CPU time 189.23 seconds
Started Feb 25 01:59:53 PM PST 24
Finished Feb 25 02:03:03 PM PST 24
Peak memory 238512 kb
Host smart-66e8513c-176c-411c-a6a3-c007f899c101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468665655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.2468665655 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_sideload/latest


Test location /workspace/coverage/default/32.kmac_smoke.2565385336
Short name T309
Test name
Test status
Simulation time 737241773 ps
CPU time 32.77 seconds
Started Feb 25 01:59:52 PM PST 24
Finished Feb 25 02:00:25 PM PST 24
Peak memory 219668 kb
Host smart-8dec0aab-86b1-48d6-802e-2a7d0ba09b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565385336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.2565385336 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_smoke/latest


Test location /workspace/coverage/default/32.kmac_stress_all.3138267469
Short name T447
Test name
Test status
Simulation time 170431257894 ps
CPU time 1735.69 seconds
Started Feb 25 02:00:08 PM PST 24
Finished Feb 25 02:29:04 PM PST 24
Peak memory 317528 kb
Host smart-9463389d-6e1d-4733-80f7-34d8863aa251
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3138267469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.3138267469 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_stress_all/latest


Test location /workspace/coverage/default/32.kmac_test_vectors_kmac.1211311663
Short name T344
Test name
Test status
Simulation time 4933500084 ps
CPU time 8.14 seconds
Started Feb 25 01:59:59 PM PST 24
Finished Feb 25 02:00:08 PM PST 24
Peak memory 218536 kb
Host smart-afd768af-7eb2-4ab3-aead-9feb35501961
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211311663 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.kmac_test_vectors_kmac.1211311663 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/32.kmac_test_vectors_kmac_xof.87076027
Short name T941
Test name
Test status
Simulation time 315559529 ps
CPU time 6.57 seconds
Started Feb 25 01:59:58 PM PST 24
Finished Feb 25 02:00:05 PM PST 24
Peak memory 219896 kb
Host smart-eabf7086-7707-4ffa-a3ca-a2d43024ef99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87076027 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.kmac_test_vectors_kmac_xof.87076027 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_224.3930012746
Short name T692
Test name
Test status
Simulation time 42656872735 ps
CPU time 2091.64 seconds
Started Feb 25 01:59:53 PM PST 24
Finished Feb 25 02:34:45 PM PST 24
Peak memory 402988 kb
Host smart-f2b8960e-b224-43ee-830c-0ffa2d22f6ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3930012746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_224.3930012746 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_256.351400748
Short name T919
Test name
Test status
Simulation time 20134883672 ps
CPU time 1968.21 seconds
Started Feb 25 01:59:57 PM PST 24
Finished Feb 25 02:32:46 PM PST 24
Peak memory 389248 kb
Host smart-afc904d1-a416-4991-b1f6-aee58ad9ef5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=351400748 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_256.351400748 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_384.1786402670
Short name T922
Test name
Test status
Simulation time 61378986055 ps
CPU time 1729.65 seconds
Started Feb 25 01:59:58 PM PST 24
Finished Feb 25 02:28:49 PM PST 24
Peak memory 340936 kb
Host smart-ce84b55a-b3e9-460a-b9e6-693912b5e059
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1786402670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_384.1786402670 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_512.2583629458
Short name T704
Test name
Test status
Simulation time 34348145473 ps
CPU time 1365.93 seconds
Started Feb 25 02:00:07 PM PST 24
Finished Feb 25 02:22:53 PM PST 24
Peak memory 304068 kb
Host smart-3d967624-6781-477d-bd65-46caf9f151c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2583629458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_512.2583629458 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/32.kmac_test_vectors_shake_128.988092041
Short name T374
Test name
Test status
Simulation time 64906637026 ps
CPU time 5374.6 seconds
Started Feb 25 01:59:58 PM PST 24
Finished Feb 25 03:29:34 PM PST 24
Peak memory 658464 kb
Host smart-11aea940-e12c-42c6-8752-ddf94b2227fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=988092041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_128.988092041 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/32.kmac_test_vectors_shake_256.1178026224
Short name T32
Test name
Test status
Simulation time 235562815692 ps
CPU time 5251.91 seconds
Started Feb 25 02:00:07 PM PST 24
Finished Feb 25 03:27:40 PM PST 24
Peak memory 575076 kb
Host smart-a909691e-401b-454f-9508-b447c1f8c502
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1178026224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_256.1178026224 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/33.kmac_alert_test.3387181027
Short name T267
Test name
Test status
Simulation time 29776019 ps
CPU time 0.99 seconds
Started Feb 25 02:00:32 PM PST 24
Finished Feb 25 02:00:33 PM PST 24
Peak memory 218200 kb
Host smart-df88c005-8b0c-426c-828e-9f6274b49e88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387181027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.3387181027 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_alert_test/latest


Test location /workspace/coverage/default/33.kmac_app.771645150
Short name T502
Test name
Test status
Simulation time 34806998609 ps
CPU time 177.74 seconds
Started Feb 25 02:00:41 PM PST 24
Finished Feb 25 02:03:40 PM PST 24
Peak memory 239780 kb
Host smart-10e6758e-812e-431b-b6fc-ed2de8b92ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771645150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.771645150 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_app/latest


Test location /workspace/coverage/default/33.kmac_burst_write.927957070
Short name T391
Test name
Test status
Simulation time 28585750948 ps
CPU time 1574.36 seconds
Started Feb 25 02:00:10 PM PST 24
Finished Feb 25 02:26:25 PM PST 24
Peak memory 240220 kb
Host smart-441b7008-5bc8-422f-b886-fe921080a62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927957070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.927957070 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_burst_write/latest


Test location /workspace/coverage/default/33.kmac_entropy_refresh.622635387
Short name T357
Test name
Test status
Simulation time 4655561443 ps
CPU time 226.89 seconds
Started Feb 25 02:00:31 PM PST 24
Finished Feb 25 02:04:18 PM PST 24
Peak memory 245280 kb
Host smart-4bde1a76-b732-4a02-afee-ef3c472aedd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622635387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.622635387 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/33.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/33.kmac_error.1476149119
Short name T168
Test name
Test status
Simulation time 3143242929 ps
CPU time 264.89 seconds
Started Feb 25 02:00:28 PM PST 24
Finished Feb 25 02:04:53 PM PST 24
Peak memory 256896 kb
Host smart-18344e78-7396-4563-8eaa-fabd30c69d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476149119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.1476149119 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_error/latest


Test location /workspace/coverage/default/33.kmac_key_error.2606564470
Short name T331
Test name
Test status
Simulation time 1080088429 ps
CPU time 6.99 seconds
Started Feb 25 02:00:26 PM PST 24
Finished Feb 25 02:00:33 PM PST 24
Peak memory 218308 kb
Host smart-1ef7a4e1-7a91-4567-a831-89490f166d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606564470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.2606564470 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_key_error/latest


Test location /workspace/coverage/default/33.kmac_lc_escalation.3290131521
Short name T16
Test name
Test status
Simulation time 2450515840 ps
CPU time 17.27 seconds
Started Feb 25 02:00:32 PM PST 24
Finished Feb 25 02:00:50 PM PST 24
Peak memory 231408 kb
Host smart-8e8c475f-2ebd-475c-bfcf-1c130154c6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290131521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.3290131521 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/33.kmac_lc_escalation/latest


Test location /workspace/coverage/default/33.kmac_long_msg_and_output.2400589069
Short name T893
Test name
Test status
Simulation time 19617023435 ps
CPU time 485.71 seconds
Started Feb 25 02:00:12 PM PST 24
Finished Feb 25 02:08:18 PM PST 24
Peak memory 261612 kb
Host smart-7de15daa-e2b8-4eea-912d-e7e5a73f8ea7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400589069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_a
nd_output.2400589069 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/33.kmac_sideload.1155516338
Short name T851
Test name
Test status
Simulation time 31787725123 ps
CPU time 389.85 seconds
Started Feb 25 02:00:11 PM PST 24
Finished Feb 25 02:06:41 PM PST 24
Peak memory 250720 kb
Host smart-1cd5119e-0e60-4f5e-aba3-ca780eb1d898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155516338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.1155516338 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_sideload/latest


Test location /workspace/coverage/default/33.kmac_smoke.2238787034
Short name T904
Test name
Test status
Simulation time 1563112665 ps
CPU time 16.37 seconds
Started Feb 25 02:00:11 PM PST 24
Finished Feb 25 02:00:27 PM PST 24
Peak memory 226032 kb
Host smart-601bdc4c-a127-4a81-a6e9-41cfec9f2ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238787034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.2238787034 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_smoke/latest


Test location /workspace/coverage/default/33.kmac_stress_all.739640627
Short name T979
Test name
Test status
Simulation time 31069557262 ps
CPU time 2444.83 seconds
Started Feb 25 02:00:29 PM PST 24
Finished Feb 25 02:41:14 PM PST 24
Peak memory 398888 kb
Host smart-a17582ca-b3d6-4743-9794-3024aae5acf1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=739640627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.739640627 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_stress_all/latest


Test location /workspace/coverage/default/33.kmac_test_vectors_kmac.3377883122
Short name T414
Test name
Test status
Simulation time 112098583 ps
CPU time 5.94 seconds
Started Feb 25 02:00:32 PM PST 24
Finished Feb 25 02:00:38 PM PST 24
Peak memory 219584 kb
Host smart-c6e04009-b2c1-479a-a09e-14e9c3e9259d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377883122 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.kmac_test_vectors_kmac.3377883122 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/33.kmac_test_vectors_kmac_xof.836854330
Short name T404
Test name
Test status
Simulation time 446149076 ps
CPU time 5.62 seconds
Started Feb 25 02:00:29 PM PST 24
Finished Feb 25 02:00:35 PM PST 24
Peak memory 219744 kb
Host smart-0e9e2689-b836-4e96-a113-68379e0803ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836854330 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.kmac_test_vectors_kmac_xof.836854330 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_224.1043804730
Short name T520
Test name
Test status
Simulation time 271661384910 ps
CPU time 2401.72 seconds
Started Feb 25 02:00:10 PM PST 24
Finished Feb 25 02:40:12 PM PST 24
Peak memory 396608 kb
Host smart-60cef9b7-12e3-412a-a0a9-fbe1f9e6f285
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1043804730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_224.1043804730 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_256.69133890
Short name T679
Test name
Test status
Simulation time 33377945360 ps
CPU time 1931.85 seconds
Started Feb 25 02:00:10 PM PST 24
Finished Feb 25 02:32:22 PM PST 24
Peak memory 389188 kb
Host smart-172c123e-1948-4d38-a313-80afde13f2ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=69133890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_256.69133890 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_384.3781251024
Short name T239
Test name
Test status
Simulation time 64872758147 ps
CPU time 1590.61 seconds
Started Feb 25 02:00:29 PM PST 24
Finished Feb 25 02:27:00 PM PST 24
Peak memory 344488 kb
Host smart-feb5e56e-ce35-49af-95a0-fd4b608b45e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3781251024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_384.3781251024 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_512.888551765
Short name T747
Test name
Test status
Simulation time 41801706258 ps
CPU time 1308.66 seconds
Started Feb 25 02:00:29 PM PST 24
Finished Feb 25 02:22:18 PM PST 24
Peak memory 303356 kb
Host smart-2c7bf245-e58a-4c26-bf55-6a7c76e0de5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=888551765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_512.888551765 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/33.kmac_test_vectors_shake_128.1228623870
Short name T370
Test name
Test status
Simulation time 184663608882 ps
CPU time 6086.05 seconds
Started Feb 25 02:00:28 PM PST 24
Finished Feb 25 03:41:55 PM PST 24
Peak memory 656408 kb
Host smart-5645ec2b-c934-4e0f-8aac-820c3529609d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1228623870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_128.1228623870 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/33.kmac_test_vectors_shake_256.3768954471
Short name T659
Test name
Test status
Simulation time 54700966920 ps
CPU time 4375.36 seconds
Started Feb 25 02:00:41 PM PST 24
Finished Feb 25 03:13:38 PM PST 24
Peak memory 579892 kb
Host smart-803cd825-5959-4a4d-933c-669047f2c3d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3768954471 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_256.3768954471 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/34.kmac_alert_test.3095043160
Short name T542
Test name
Test status
Simulation time 33205974 ps
CPU time 0.9 seconds
Started Feb 25 02:00:40 PM PST 24
Finished Feb 25 02:00:42 PM PST 24
Peak memory 219224 kb
Host smart-929716d2-06a0-4959-afbe-fe5249b46493
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095043160 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.3095043160 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_alert_test/latest


Test location /workspace/coverage/default/34.kmac_app.906154361
Short name T793
Test name
Test status
Simulation time 16319314274 ps
CPU time 207.94 seconds
Started Feb 25 02:00:32 PM PST 24
Finished Feb 25 02:04:01 PM PST 24
Peak memory 242520 kb
Host smart-515367b3-f839-4087-8871-434a91bcc1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906154361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.906154361 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_app/latest


Test location /workspace/coverage/default/34.kmac_burst_write.3540578243
Short name T791
Test name
Test status
Simulation time 37045325951 ps
CPU time 765.59 seconds
Started Feb 25 02:00:33 PM PST 24
Finished Feb 25 02:13:19 PM PST 24
Peak memory 237600 kb
Host smart-5644b140-4b22-4747-94d4-f1e3654dbaf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540578243 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.3540578243 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_burst_write/latest


Test location /workspace/coverage/default/34.kmac_entropy_refresh.1412526601
Short name T578
Test name
Test status
Simulation time 2295049416 ps
CPU time 84.33 seconds
Started Feb 25 02:00:41 PM PST 24
Finished Feb 25 02:02:07 PM PST 24
Peak memory 239268 kb
Host smart-64366a5c-df7c-4d6a-bb60-e478cd28d908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412526601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.1412526601 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/34.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/34.kmac_error.2182446056
Short name T552
Test name
Test status
Simulation time 5617226787 ps
CPU time 456.26 seconds
Started Feb 25 02:00:33 PM PST 24
Finished Feb 25 02:08:09 PM PST 24
Peak memory 270088 kb
Host smart-da470bf9-8552-4ac1-90be-deb06c9b5e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182446056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.2182446056 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_error/latest


Test location /workspace/coverage/default/34.kmac_key_error.4106477666
Short name T748
Test name
Test status
Simulation time 427173103 ps
CPU time 3.22 seconds
Started Feb 25 02:00:42 PM PST 24
Finished Feb 25 02:00:46 PM PST 24
Peak memory 218296 kb
Host smart-4864a25e-980c-4c5b-be8e-eccd3dcd87f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106477666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.4106477666 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_key_error/latest


Test location /workspace/coverage/default/34.kmac_lc_escalation.809012479
Short name T879
Test name
Test status
Simulation time 4996544521 ps
CPU time 15.43 seconds
Started Feb 25 02:00:41 PM PST 24
Finished Feb 25 02:00:56 PM PST 24
Peak memory 234896 kb
Host smart-43fede58-4dd8-443a-b845-ba5c173cca59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809012479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.809012479 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/34.kmac_lc_escalation/latest


Test location /workspace/coverage/default/34.kmac_long_msg_and_output.4103166952
Short name T594
Test name
Test status
Simulation time 183157890018 ps
CPU time 1916 seconds
Started Feb 25 02:00:28 PM PST 24
Finished Feb 25 02:32:24 PM PST 24
Peak memory 397924 kb
Host smart-7ef8d5f6-a635-4744-be0b-c049acdd0f8c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103166952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_a
nd_output.4103166952 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/34.kmac_sideload.1806860593
Short name T132
Test name
Test status
Simulation time 22525801615 ps
CPU time 255.77 seconds
Started Feb 25 02:00:32 PM PST 24
Finished Feb 25 02:04:48 PM PST 24
Peak memory 243092 kb
Host smart-9d6ab3ae-3791-4eaa-aa82-aeb8cb119cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806860593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.1806860593 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_sideload/latest


Test location /workspace/coverage/default/34.kmac_smoke.2944632056
Short name T668
Test name
Test status
Simulation time 17551876524 ps
CPU time 93.76 seconds
Started Feb 25 02:00:30 PM PST 24
Finished Feb 25 02:02:04 PM PST 24
Peak memory 226540 kb
Host smart-ef44deef-dec7-4ba2-ab6a-c8167a031b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944632056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.2944632056 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_smoke/latest


Test location /workspace/coverage/default/34.kmac_stress_all.2951499990
Short name T138
Test name
Test status
Simulation time 497445354 ps
CPU time 13.43 seconds
Started Feb 25 02:00:43 PM PST 24
Finished Feb 25 02:00:57 PM PST 24
Peak memory 234080 kb
Host smart-c9aedc14-b408-4f30-b820-3ad2d17b00a5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2951499990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.2951499990 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_stress_all/latest


Test location /workspace/coverage/default/34.kmac_test_vectors_kmac.1342356693
Short name T282
Test name
Test status
Simulation time 1100813742 ps
CPU time 7.22 seconds
Started Feb 25 02:00:38 PM PST 24
Finished Feb 25 02:00:46 PM PST 24
Peak memory 218252 kb
Host smart-1930e078-5c66-465b-91cb-c2a58dadbae7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342356693 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.kmac_test_vectors_kmac.1342356693 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/34.kmac_test_vectors_kmac_xof.1211498640
Short name T770
Test name
Test status
Simulation time 199852346 ps
CPU time 6.23 seconds
Started Feb 25 02:00:31 PM PST 24
Finished Feb 25 02:00:38 PM PST 24
Peak memory 219836 kb
Host smart-85f40107-037c-40f2-89cf-a973f9cf215c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211498640 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.kmac_test_vectors_kmac_xof.1211498640 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_224.1646134024
Short name T796
Test name
Test status
Simulation time 125146305452 ps
CPU time 2200.43 seconds
Started Feb 25 02:00:32 PM PST 24
Finished Feb 25 02:37:14 PM PST 24
Peak memory 381252 kb
Host smart-cef13b48-b2a6-4205-8b5c-0e6fbdd723c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1646134024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_224.1646134024 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_256.1854309721
Short name T355
Test name
Test status
Simulation time 163912978157 ps
CPU time 2295.2 seconds
Started Feb 25 02:00:33 PM PST 24
Finished Feb 25 02:38:49 PM PST 24
Peak memory 391536 kb
Host smart-dbefaf04-92d7-4686-85e6-441f7e6e739e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1854309721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_256.1854309721 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_384.2139225295
Short name T1045
Test name
Test status
Simulation time 19175051107 ps
CPU time 1508.21 seconds
Started Feb 25 02:00:31 PM PST 24
Finished Feb 25 02:25:39 PM PST 24
Peak memory 339536 kb
Host smart-029a8e5d-742c-4e2a-b3f5-64935b2984b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2139225295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_384.2139225295 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_512.2496782554
Short name T265
Test name
Test status
Simulation time 101090672561 ps
CPU time 1396.74 seconds
Started Feb 25 02:00:32 PM PST 24
Finished Feb 25 02:23:49 PM PST 24
Peak memory 299164 kb
Host smart-f5990b90-3790-4f69-8342-2fb618bc41fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2496782554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_512.2496782554 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/34.kmac_test_vectors_shake_128.3674113145
Short name T815
Test name
Test status
Simulation time 245037885521 ps
CPU time 5146.16 seconds
Started Feb 25 02:00:41 PM PST 24
Finished Feb 25 03:26:29 PM PST 24
Peak memory 674520 kb
Host smart-7cf0d4c5-9439-4c49-8675-43ff5bef4ec0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3674113145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_128.3674113145 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/34.kmac_test_vectors_shake_256.3312886557
Short name T809
Test name
Test status
Simulation time 878358706429 ps
CPU time 5644.12 seconds
Started Feb 25 02:00:33 PM PST 24
Finished Feb 25 03:34:38 PM PST 24
Peak memory 579336 kb
Host smart-72a3206c-70e3-43e8-99db-8f46d2904c4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3312886557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_256.3312886557 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/35.kmac_alert_test.3882352671
Short name T415
Test name
Test status
Simulation time 21943675 ps
CPU time 0.83 seconds
Started Feb 25 02:01:05 PM PST 24
Finished Feb 25 02:01:07 PM PST 24
Peak memory 219324 kb
Host smart-76b8fafd-8caa-4879-9d18-c9f85472c492
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882352671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.3882352671 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_alert_test/latest


Test location /workspace/coverage/default/35.kmac_app.3899332541
Short name T487
Test name
Test status
Simulation time 37345511364 ps
CPU time 300.35 seconds
Started Feb 25 02:00:55 PM PST 24
Finished Feb 25 02:05:55 PM PST 24
Peak memory 251300 kb
Host smart-f09435e3-39d8-4da6-bf25-7d055e21f9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899332541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.3899332541 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_app/latest


Test location /workspace/coverage/default/35.kmac_burst_write.214235764
Short name T719
Test name
Test status
Simulation time 49410692910 ps
CPU time 463.03 seconds
Started Feb 25 02:00:43 PM PST 24
Finished Feb 25 02:08:26 PM PST 24
Peak memory 242016 kb
Host smart-7557872b-c473-4fe0-a9a5-534f9836aa2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214235764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.214235764 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_burst_write/latest


Test location /workspace/coverage/default/35.kmac_entropy_refresh.3493474785
Short name T503
Test name
Test status
Simulation time 18822079306 ps
CPU time 227.51 seconds
Started Feb 25 02:00:59 PM PST 24
Finished Feb 25 02:04:46 PM PST 24
Peak memory 244484 kb
Host smart-67fff2a7-b608-4522-a511-369bfe4230a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493474785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.3493474785 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/35.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/35.kmac_error.2253478272
Short name T291
Test name
Test status
Simulation time 1218811655 ps
CPU time 100.61 seconds
Started Feb 25 02:00:52 PM PST 24
Finished Feb 25 02:02:33 PM PST 24
Peak memory 251104 kb
Host smart-1186d989-873a-44e7-a775-dc07c0a2269d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253478272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.2253478272 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_error/latest


Test location /workspace/coverage/default/35.kmac_key_error.2089286753
Short name T35
Test name
Test status
Simulation time 897048486 ps
CPU time 2.15 seconds
Started Feb 25 02:00:52 PM PST 24
Finished Feb 25 02:00:55 PM PST 24
Peak memory 218396 kb
Host smart-c6a076f4-ed1d-48f3-ae4e-01bae4e6c8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089286753 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.2089286753 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_key_error/latest


Test location /workspace/coverage/default/35.kmac_lc_escalation.726697037
Short name T66
Test name
Test status
Simulation time 74401501 ps
CPU time 1.51 seconds
Started Feb 25 02:00:51 PM PST 24
Finished Feb 25 02:00:53 PM PST 24
Peak memory 219692 kb
Host smart-2d97d766-e056-4106-88c2-236a81dccc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726697037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.726697037 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/35.kmac_lc_escalation/latest


Test location /workspace/coverage/default/35.kmac_long_msg_and_output.3882547957
Short name T858
Test name
Test status
Simulation time 77881407 ps
CPU time 8.99 seconds
Started Feb 25 02:00:43 PM PST 24
Finished Feb 25 02:00:52 PM PST 24
Peak memory 219900 kb
Host smart-59d06612-f70c-4909-a046-227c912c58aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882547957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_a
nd_output.3882547957 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/35.kmac_sideload.2794594470
Short name T684
Test name
Test status
Simulation time 4557845679 ps
CPU time 203.99 seconds
Started Feb 25 02:00:41 PM PST 24
Finished Feb 25 02:04:06 PM PST 24
Peak memory 243036 kb
Host smart-728001d8-e588-4405-a93d-f3d296e106fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794594470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.2794594470 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_sideload/latest


Test location /workspace/coverage/default/35.kmac_smoke.1426175859
Short name T214
Test name
Test status
Simulation time 3502226109 ps
CPU time 55.18 seconds
Started Feb 25 02:00:42 PM PST 24
Finished Feb 25 02:01:37 PM PST 24
Peak memory 226648 kb
Host smart-f93a84bb-10b3-4b5c-8e87-5ea4be67e007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426175859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.1426175859 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_smoke/latest


Test location /workspace/coverage/default/35.kmac_stress_all.1634507091
Short name T53
Test name
Test status
Simulation time 138915775628 ps
CPU time 3318.45 seconds
Started Feb 25 02:01:05 PM PST 24
Finished Feb 25 02:56:25 PM PST 24
Peak memory 473416 kb
Host smart-78ddef86-558a-4cdb-8d27-36704259d709
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1634507091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.1634507091 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_stress_all/latest


Test location /workspace/coverage/default/35.kmac_test_vectors_kmac.2586467388
Short name T286
Test name
Test status
Simulation time 275725968 ps
CPU time 6.35 seconds
Started Feb 25 02:00:53 PM PST 24
Finished Feb 25 02:01:00 PM PST 24
Peak memory 219808 kb
Host smart-d18b54fc-9351-4e7c-9e7e-facf076c6869
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586467388 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.kmac_test_vectors_kmac.2586467388 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/35.kmac_test_vectors_kmac_xof.577357773
Short name T926
Test name
Test status
Simulation time 266870203 ps
CPU time 6.97 seconds
Started Feb 25 02:00:59 PM PST 24
Finished Feb 25 02:01:06 PM PST 24
Peak memory 219728 kb
Host smart-d3b161da-6b7e-4735-8d18-16645a4fff6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577357773 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.kmac_test_vectors_kmac_xof.577357773 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_224.2052012809
Short name T1047
Test name
Test status
Simulation time 40486473546 ps
CPU time 2188.94 seconds
Started Feb 25 02:00:41 PM PST 24
Finished Feb 25 02:37:11 PM PST 24
Peak memory 395276 kb
Host smart-9df3173f-5251-4104-b82b-cbc77995ee7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2052012809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_224.2052012809 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_256.555799544
Short name T1037
Test name
Test status
Simulation time 19200662788 ps
CPU time 2002.64 seconds
Started Feb 25 02:00:42 PM PST 24
Finished Feb 25 02:34:05 PM PST 24
Peak memory 386756 kb
Host smart-badd7573-f070-41c6-a0ac-120f3863c269
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=555799544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_256.555799544 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_384.3916302527
Short name T1024
Test name
Test status
Simulation time 70218657277 ps
CPU time 1801.01 seconds
Started Feb 25 02:00:42 PM PST 24
Finished Feb 25 02:30:43 PM PST 24
Peak memory 336088 kb
Host smart-3780be95-899a-403f-ae1e-b33b0eae5fa8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3916302527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_384.3916302527 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_512.104693607
Short name T1002
Test name
Test status
Simulation time 34144521687 ps
CPU time 1164.39 seconds
Started Feb 25 02:00:56 PM PST 24
Finished Feb 25 02:20:20 PM PST 24
Peak memory 301988 kb
Host smart-9bc06c7f-2cde-4929-8375-1bccac7c4905
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=104693607 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_512.104693607 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/35.kmac_test_vectors_shake_128.518159617
Short name T683
Test name
Test status
Simulation time 76134282613 ps
CPU time 5272.56 seconds
Started Feb 25 02:00:52 PM PST 24
Finished Feb 25 03:28:45 PM PST 24
Peak memory 661536 kb
Host smart-0e2845cb-0426-4ed0-8fe8-dffd372ce59e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=518159617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_128.518159617 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/35.kmac_test_vectors_shake_256.3596696346
Short name T731
Test name
Test status
Simulation time 333305327180 ps
CPU time 4895.82 seconds
Started Feb 25 02:00:53 PM PST 24
Finished Feb 25 03:22:30 PM PST 24
Peak memory 581372 kb
Host smart-3d0c1f62-145e-4cd2-bb5a-5bae50592340
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3596696346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_256.3596696346 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/36.kmac_alert_test.625893245
Short name T765
Test name
Test status
Simulation time 14420079 ps
CPU time 0.79 seconds
Started Feb 25 02:01:13 PM PST 24
Finished Feb 25 02:01:14 PM PST 24
Peak memory 218036 kb
Host smart-deb1a582-6869-42e8-b7b5-b0a6690813b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625893245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.625893245 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/36.kmac_alert_test/latest


Test location /workspace/coverage/default/36.kmac_app.3782849019
Short name T1020
Test name
Test status
Simulation time 3303107682 ps
CPU time 102.11 seconds
Started Feb 25 02:01:15 PM PST 24
Finished Feb 25 02:02:57 PM PST 24
Peak memory 234464 kb
Host smart-d233d449-cf1c-4a11-b853-2b6a1bbaf61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782849019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.3782849019 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_app/latest


Test location /workspace/coverage/default/36.kmac_burst_write.3265695269
Short name T251
Test name
Test status
Simulation time 5531509577 ps
CPU time 662.72 seconds
Started Feb 25 02:01:06 PM PST 24
Finished Feb 25 02:12:09 PM PST 24
Peak memory 241252 kb
Host smart-75059d34-277a-49f3-a2e9-fe4531d9ffdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265695269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.3265695269 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_burst_write/latest


Test location /workspace/coverage/default/36.kmac_entropy_refresh.415823886
Short name T456
Test name
Test status
Simulation time 1926164275 ps
CPU time 75.87 seconds
Started Feb 25 02:01:14 PM PST 24
Finished Feb 25 02:02:30 PM PST 24
Peak memory 237736 kb
Host smart-52e6f1ff-0825-4359-b7d3-f6686534efc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415823886 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.415823886 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/36.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/36.kmac_error.3337707642
Short name T1040
Test name
Test status
Simulation time 36428467784 ps
CPU time 393.6 seconds
Started Feb 25 02:01:14 PM PST 24
Finished Feb 25 02:07:48 PM PST 24
Peak memory 259412 kb
Host smart-80d171ea-9e00-45e2-8383-4fdec1c695e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337707642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.3337707642 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_error/latest


Test location /workspace/coverage/default/36.kmac_key_error.2466029986
Short name T544
Test name
Test status
Simulation time 1142159234 ps
CPU time 6.22 seconds
Started Feb 25 02:01:15 PM PST 24
Finished Feb 25 02:01:22 PM PST 24
Peak memory 218288 kb
Host smart-4c4af2bb-f77c-4e1f-8e87-83230fb94200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466029986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.2466029986 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_key_error/latest


Test location /workspace/coverage/default/36.kmac_lc_escalation.3431214524
Short name T25
Test name
Test status
Simulation time 45713525 ps
CPU time 1.59 seconds
Started Feb 25 02:01:12 PM PST 24
Finished Feb 25 02:01:15 PM PST 24
Peak memory 219392 kb
Host smart-7a83b99d-b7c7-46fc-b384-606956341ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431214524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.3431214524 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/36.kmac_lc_escalation/latest


Test location /workspace/coverage/default/36.kmac_long_msg_and_output.1972638367
Short name T806
Test name
Test status
Simulation time 172761027073 ps
CPU time 3378.58 seconds
Started Feb 25 02:01:07 PM PST 24
Finished Feb 25 02:57:27 PM PST 24
Peak memory 471012 kb
Host smart-180446ba-521d-43be-a15f-cee954b480a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972638367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_a
nd_output.1972638367 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/36.kmac_sideload.4226198755
Short name T984
Test name
Test status
Simulation time 22106995143 ps
CPU time 536.53 seconds
Started Feb 25 02:01:08 PM PST 24
Finished Feb 25 02:10:06 PM PST 24
Peak memory 257036 kb
Host smart-489df6ed-4585-491e-b12b-849f7162f5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226198755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.4226198755 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_sideload/latest


Test location /workspace/coverage/default/36.kmac_smoke.517714201
Short name T302
Test name
Test status
Simulation time 2635109915 ps
CPU time 48.98 seconds
Started Feb 25 02:01:05 PM PST 24
Finished Feb 25 02:01:55 PM PST 24
Peak memory 226524 kb
Host smart-e1e3f382-2f2a-43d8-8969-3b45e037cc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517714201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.517714201 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_smoke/latest


Test location /workspace/coverage/default/36.kmac_stress_all.2231884416
Short name T761
Test name
Test status
Simulation time 11041167967 ps
CPU time 255.86 seconds
Started Feb 25 02:01:14 PM PST 24
Finished Feb 25 02:05:30 PM PST 24
Peak memory 260664 kb
Host smart-fcef64ea-75f4-4835-99b0-11c21d9b43f1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2231884416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.2231884416 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_stress_all/latest


Test location /workspace/coverage/default/36.kmac_stress_all_with_rand_reset.2136107776
Short name T151
Test name
Test status
Simulation time 47743087641 ps
CPU time 470.38 seconds
Started Feb 25 02:01:12 PM PST 24
Finished Feb 25 02:09:04 PM PST 24
Peak memory 275948 kb
Host smart-3b048abd-958d-4e3e-9068-cea34fa9ab65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2136107776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all_with_rand_reset.2136107776 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/36.kmac_test_vectors_kmac.692567209
Short name T601
Test name
Test status
Simulation time 503760485 ps
CPU time 7.32 seconds
Started Feb 25 02:01:05 PM PST 24
Finished Feb 25 02:01:14 PM PST 24
Peak memory 218460 kb
Host smart-dace8700-ba0d-4e42-af1e-941dbf5af5a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692567209 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.kmac_test_vectors_kmac.692567209 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/36.kmac_test_vectors_kmac_xof.3414563263
Short name T673
Test name
Test status
Simulation time 1110768032 ps
CPU time 6.74 seconds
Started Feb 25 02:01:12 PM PST 24
Finished Feb 25 02:01:20 PM PST 24
Peak memory 219528 kb
Host smart-f89008ca-d7e0-4360-9830-183b6c2f125a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414563263 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.kmac_test_vectors_kmac_xof.3414563263 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_224.2531328951
Short name T378
Test name
Test status
Simulation time 65441645214 ps
CPU time 2196.83 seconds
Started Feb 25 02:01:05 PM PST 24
Finished Feb 25 02:37:43 PM PST 24
Peak memory 396996 kb
Host smart-29dfc65e-a1c8-49f7-85f7-4e499a35831a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2531328951 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_224.2531328951 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_256.1349540215
Short name T160
Test name
Test status
Simulation time 216408552928 ps
CPU time 2140.06 seconds
Started Feb 25 02:01:05 PM PST 24
Finished Feb 25 02:36:47 PM PST 24
Peak memory 394744 kb
Host smart-834a60a3-6d77-4fe4-993b-8992616548c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1349540215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_256.1349540215 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_384.2551782246
Short name T615
Test name
Test status
Simulation time 47849733709 ps
CPU time 1881.1 seconds
Started Feb 25 02:01:07 PM PST 24
Finished Feb 25 02:32:30 PM PST 24
Peak memory 339756 kb
Host smart-2b609755-f5dc-43c3-a4e0-5ca1ae40c1d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2551782246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_384.2551782246 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_512.1808102982
Short name T778
Test name
Test status
Simulation time 36333685686 ps
CPU time 1398.23 seconds
Started Feb 25 02:01:07 PM PST 24
Finished Feb 25 02:24:27 PM PST 24
Peak memory 305536 kb
Host smart-39f3ab2b-08b5-48c6-8dbe-1a9cafaea15a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1808102982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_512.1808102982 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/36.kmac_test_vectors_shake_128.2385208159
Short name T255
Test name
Test status
Simulation time 121441796265 ps
CPU time 5295.88 seconds
Started Feb 25 02:01:05 PM PST 24
Finished Feb 25 03:29:23 PM PST 24
Peak memory 642556 kb
Host smart-72e57c2c-4d2b-4545-aead-c9e6298389ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2385208159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_128.2385208159 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/36.kmac_test_vectors_shake_256.70003389
Short name T462
Test name
Test status
Simulation time 435016718663 ps
CPU time 5559.9 seconds
Started Feb 25 02:01:07 PM PST 24
Finished Feb 25 03:33:49 PM PST 24
Peak memory 566508 kb
Host smart-1ae437ca-111e-4637-9eb5-6b5e9a8e019f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=70003389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_256.70003389 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/37.kmac_alert_test.1145942476
Short name T101
Test name
Test status
Simulation time 17289612 ps
CPU time 0.84 seconds
Started Feb 25 02:01:31 PM PST 24
Finished Feb 25 02:01:32 PM PST 24
Peak memory 219224 kb
Host smart-3049816b-e847-4e3e-a4e5-7a99b56dd825
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145942476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.1145942476 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_alert_test/latest


Test location /workspace/coverage/default/37.kmac_app.3502192262
Short name T995
Test name
Test status
Simulation time 39702690568 ps
CPU time 486.49 seconds
Started Feb 25 02:01:19 PM PST 24
Finished Feb 25 02:09:26 PM PST 24
Peak memory 255612 kb
Host smart-e763cc8c-eb23-435e-a732-da456a0695b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502192262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.3502192262 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_app/latest


Test location /workspace/coverage/default/37.kmac_entropy_refresh.729620065
Short name T9
Test name
Test status
Simulation time 2320441887 ps
CPU time 56.99 seconds
Started Feb 25 02:01:18 PM PST 24
Finished Feb 25 02:02:16 PM PST 24
Peak memory 228436 kb
Host smart-9d3beccf-8a61-476e-a0ab-b5ff54947ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729620065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.729620065 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/37.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/37.kmac_error.2050308491
Short name T359
Test name
Test status
Simulation time 84086832984 ps
CPU time 579.96 seconds
Started Feb 25 02:01:19 PM PST 24
Finished Feb 25 02:11:00 PM PST 24
Peak memory 268436 kb
Host smart-659aa96b-c969-45c2-a120-7084ef34e794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050308491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.2050308491 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_error/latest


Test location /workspace/coverage/default/37.kmac_key_error.2926008945
Short name T477
Test name
Test status
Simulation time 2258089221 ps
CPU time 3.69 seconds
Started Feb 25 02:01:30 PM PST 24
Finished Feb 25 02:01:34 PM PST 24
Peak memory 218160 kb
Host smart-b28543c5-db25-4231-99c6-c3951d83b42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926008945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.2926008945 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_key_error/latest


Test location /workspace/coverage/default/37.kmac_lc_escalation.1841570667
Short name T938
Test name
Test status
Simulation time 43098726 ps
CPU time 1.52 seconds
Started Feb 25 02:01:30 PM PST 24
Finished Feb 25 02:01:32 PM PST 24
Peak memory 219780 kb
Host smart-216d0097-4e1d-46ad-84e2-49a152aacdf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841570667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.1841570667 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/37.kmac_lc_escalation/latest


Test location /workspace/coverage/default/37.kmac_long_msg_and_output.2997234025
Short name T849
Test name
Test status
Simulation time 138021832808 ps
CPU time 1173.59 seconds
Started Feb 25 02:01:14 PM PST 24
Finished Feb 25 02:20:48 PM PST 24
Peak memory 320760 kb
Host smart-21afcec5-0074-4835-a841-b89556aece2f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997234025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_a
nd_output.2997234025 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/37.kmac_sideload.3903851851
Short name T369
Test name
Test status
Simulation time 2935182418 ps
CPU time 245.77 seconds
Started Feb 25 02:01:15 PM PST 24
Finished Feb 25 02:05:21 PM PST 24
Peak memory 243812 kb
Host smart-df870b03-f151-48f6-9b96-18ed873afdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903851851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.3903851851 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_sideload/latest


Test location /workspace/coverage/default/37.kmac_smoke.1300814705
Short name T846
Test name
Test status
Simulation time 4650995015 ps
CPU time 70.15 seconds
Started Feb 25 02:01:14 PM PST 24
Finished Feb 25 02:02:25 PM PST 24
Peak memory 224716 kb
Host smart-1ea15e55-841c-42a6-9d6f-fb0c1447f2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300814705 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.1300814705 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_smoke/latest


Test location /workspace/coverage/default/37.kmac_stress_all.1963270770
Short name T406
Test name
Test status
Simulation time 250964277774 ps
CPU time 1771.92 seconds
Started Feb 25 02:01:31 PM PST 24
Finished Feb 25 02:31:03 PM PST 24
Peak memory 381448 kb
Host smart-de5afc41-b5cc-4a02-bf81-26b471423ebb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1963270770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.1963270770 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_stress_all/latest


Test location /workspace/coverage/default/37.kmac_test_vectors_kmac.647476647
Short name T194
Test name
Test status
Simulation time 1043218954 ps
CPU time 6.18 seconds
Started Feb 25 02:01:20 PM PST 24
Finished Feb 25 02:01:27 PM PST 24
Peak memory 219820 kb
Host smart-d853cc88-9698-468b-b79d-69ed299fd03c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647476647 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.kmac_test_vectors_kmac.647476647 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/37.kmac_test_vectors_kmac_xof.2418600975
Short name T284
Test name
Test status
Simulation time 822614099 ps
CPU time 6.33 seconds
Started Feb 25 02:01:18 PM PST 24
Finished Feb 25 02:01:25 PM PST 24
Peak memory 218336 kb
Host smart-cf85bc5f-65b5-4dbe-808d-a5999cb8626a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418600975 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.kmac_test_vectors_kmac_xof.2418600975 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_224.1429853449
Short name T516
Test name
Test status
Simulation time 90789018705 ps
CPU time 1897.9 seconds
Started Feb 25 02:01:21 PM PST 24
Finished Feb 25 02:33:00 PM PST 24
Peak memory 393300 kb
Host smart-fbb18d58-13ea-4a5e-b1bb-1b294fabd9c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1429853449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_224.1429853449 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_256.2342307763
Short name T392
Test name
Test status
Simulation time 80375525584 ps
CPU time 2156.12 seconds
Started Feb 25 02:01:21 PM PST 24
Finished Feb 25 02:37:18 PM PST 24
Peak memory 389940 kb
Host smart-b9b5970c-88d0-44f3-a9ff-ae85f36824f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2342307763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_256.2342307763 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_384.679217889
Short name T236
Test name
Test status
Simulation time 266210059269 ps
CPU time 1868.54 seconds
Started Feb 25 02:01:20 PM PST 24
Finished Feb 25 02:32:29 PM PST 24
Peak memory 353548 kb
Host smart-998f6953-7f2a-4713-a649-be746d70228a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=679217889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_384.679217889 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_512.2926510102
Short name T917
Test name
Test status
Simulation time 11092626693 ps
CPU time 1295.37 seconds
Started Feb 25 02:01:23 PM PST 24
Finished Feb 25 02:22:58 PM PST 24
Peak memory 303716 kb
Host smart-7d1ddf1a-87ca-48d3-9c33-bd3d17d1a456
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2926510102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_512.2926510102 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/37.kmac_test_vectors_shake_128.1260049993
Short name T1006
Test name
Test status
Simulation time 802235892975 ps
CPU time 5814.18 seconds
Started Feb 25 02:01:21 PM PST 24
Finished Feb 25 03:38:16 PM PST 24
Peak memory 661532 kb
Host smart-e408ef41-8062-4376-bcee-6708183c103d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1260049993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_128.1260049993 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/37.kmac_test_vectors_shake_256.272732531
Short name T824
Test name
Test status
Simulation time 338076682530 ps
CPU time 5729.51 seconds
Started Feb 25 02:01:20 PM PST 24
Finished Feb 25 03:36:50 PM PST 24
Peak memory 580968 kb
Host smart-0d4481c3-f389-4a7d-a192-781d9655ce5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=272732531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_256.272732531 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/38.kmac_alert_test.3764132905
Short name T663
Test name
Test status
Simulation time 108736389 ps
CPU time 0.84 seconds
Started Feb 25 02:01:59 PM PST 24
Finished Feb 25 02:02:00 PM PST 24
Peak memory 218212 kb
Host smart-44f1c059-da17-492c-aec7-93584b9b9665
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764132905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.3764132905 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_alert_test/latest


Test location /workspace/coverage/default/38.kmac_app.3552963354
Short name T215
Test name
Test status
Simulation time 56563884063 ps
CPU time 354.96 seconds
Started Feb 25 02:01:39 PM PST 24
Finished Feb 25 02:07:35 PM PST 24
Peak memory 248904 kb
Host smart-797ca690-77e4-4291-814d-e41f73697eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552963354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.3552963354 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_app/latest


Test location /workspace/coverage/default/38.kmac_burst_write.824552594
Short name T260
Test name
Test status
Simulation time 1289151553 ps
CPU time 43.77 seconds
Started Feb 25 02:01:38 PM PST 24
Finished Feb 25 02:02:22 PM PST 24
Peak memory 228092 kb
Host smart-164fcd47-7cb5-46d1-84cc-369966c34100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824552594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.824552594 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_burst_write/latest


Test location /workspace/coverage/default/38.kmac_entropy_refresh.1244196219
Short name T77
Test name
Test status
Simulation time 2167270542 ps
CPU time 52.47 seconds
Started Feb 25 02:01:42 PM PST 24
Finished Feb 25 02:02:34 PM PST 24
Peak memory 226752 kb
Host smart-04cba05e-1d15-427a-abab-d6614bb84b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244196219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.1244196219 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/38.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/38.kmac_error.4007003131
Short name T232
Test name
Test status
Simulation time 53940908023 ps
CPU time 212.15 seconds
Started Feb 25 02:01:40 PM PST 24
Finished Feb 25 02:05:12 PM PST 24
Peak memory 255608 kb
Host smart-8f88625b-b669-4027-a58a-3225b933823f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007003131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.4007003131 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_error/latest


Test location /workspace/coverage/default/38.kmac_key_error.4139178266
Short name T2
Test name
Test status
Simulation time 473496016 ps
CPU time 1.23 seconds
Started Feb 25 02:02:00 PM PST 24
Finished Feb 25 02:02:03 PM PST 24
Peak memory 218148 kb
Host smart-a56bd376-ea25-46c9-b060-808e64298dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139178266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.4139178266 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_key_error/latest


Test location /workspace/coverage/default/38.kmac_lc_escalation.3686792103
Short name T317
Test name
Test status
Simulation time 3849507590 ps
CPU time 26.59 seconds
Started Feb 25 02:01:58 PM PST 24
Finished Feb 25 02:02:24 PM PST 24
Peak memory 236040 kb
Host smart-40ed9400-62e0-43fb-ba44-41b86d161853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686792103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.3686792103 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/38.kmac_lc_escalation/latest


Test location /workspace/coverage/default/38.kmac_long_msg_and_output.2556255403
Short name T974
Test name
Test status
Simulation time 122445315282 ps
CPU time 1067.42 seconds
Started Feb 25 02:01:29 PM PST 24
Finished Feb 25 02:19:17 PM PST 24
Peak memory 307652 kb
Host smart-c0c5cfe1-91b9-41dc-b071-445d16060278
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556255403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_a
nd_output.2556255403 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/38.kmac_sideload.2668679493
Short name T363
Test name
Test status
Simulation time 27717789953 ps
CPU time 326.64 seconds
Started Feb 25 02:01:29 PM PST 24
Finished Feb 25 02:06:56 PM PST 24
Peak memory 246864 kb
Host smart-14ae7190-b0e7-495c-97af-d2f0e5d5ebbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668679493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.2668679493 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_sideload/latest


Test location /workspace/coverage/default/38.kmac_smoke.2637159644
Short name T394
Test name
Test status
Simulation time 3214788101 ps
CPU time 33.63 seconds
Started Feb 25 02:01:32 PM PST 24
Finished Feb 25 02:02:06 PM PST 24
Peak memory 226228 kb
Host smart-dbe09444-f3e5-40d9-baab-0ce24a576427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637159644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.2637159644 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_smoke/latest


Test location /workspace/coverage/default/38.kmac_stress_all.113559986
Short name T549
Test name
Test status
Simulation time 748083698534 ps
CPU time 1367.06 seconds
Started Feb 25 02:02:00 PM PST 24
Finished Feb 25 02:24:49 PM PST 24
Peak memory 373452 kb
Host smart-f4c2db13-a6ab-496d-8752-03bb1e9073a7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=113559986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.113559986 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_stress_all/latest


Test location /workspace/coverage/default/38.kmac_test_vectors_kmac.3210530754
Short name T674
Test name
Test status
Simulation time 220544756 ps
CPU time 7.44 seconds
Started Feb 25 02:01:39 PM PST 24
Finished Feb 25 02:01:47 PM PST 24
Peak memory 218336 kb
Host smart-567032e9-642b-482e-bbdd-133acf58c297
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210530754 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.kmac_test_vectors_kmac.3210530754 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/38.kmac_test_vectors_kmac_xof.4037837869
Short name T1013
Test name
Test status
Simulation time 1380575610 ps
CPU time 7.48 seconds
Started Feb 25 02:01:39 PM PST 24
Finished Feb 25 02:01:47 PM PST 24
Peak memory 219656 kb
Host smart-2a487279-db8a-49cf-9bb2-4e75b04d48e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037837869 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.kmac_test_vectors_kmac_xof.4037837869 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_224.1987917378
Short name T197
Test name
Test status
Simulation time 231939081331 ps
CPU time 2335.03 seconds
Started Feb 25 02:01:38 PM PST 24
Finished Feb 25 02:40:33 PM PST 24
Peak memory 393432 kb
Host smart-599b01fc-52ef-4a1d-946c-0c2731e27021
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1987917378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_224.1987917378 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_256.748997379
Short name T999
Test name
Test status
Simulation time 333303405667 ps
CPU time 2268.6 seconds
Started Feb 25 02:01:40 PM PST 24
Finished Feb 25 02:39:29 PM PST 24
Peak memory 390276 kb
Host smart-1ed1056e-c61f-4e00-94ad-d4d2aa798cf4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=748997379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_256.748997379 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_384.643355177
Short name T1034
Test name
Test status
Simulation time 50230536061 ps
CPU time 1888.89 seconds
Started Feb 25 02:01:40 PM PST 24
Finished Feb 25 02:33:10 PM PST 24
Peak memory 337336 kb
Host smart-baf77ef3-de18-4b3c-8492-e25229304fe4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=643355177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_384.643355177 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_512.3382638168
Short name T976
Test name
Test status
Simulation time 136310922344 ps
CPU time 1530.75 seconds
Started Feb 25 02:01:40 PM PST 24
Finished Feb 25 02:27:11 PM PST 24
Peak memory 306032 kb
Host smart-56239d08-a7ff-4b1a-a6d4-e66a413526fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3382638168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_512.3382638168 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/38.kmac_test_vectors_shake_128.1118233669
Short name T1049
Test name
Test status
Simulation time 129670738012 ps
CPU time 5079.5 seconds
Started Feb 25 02:01:40 PM PST 24
Finished Feb 25 03:26:20 PM PST 24
Peak memory 656820 kb
Host smart-e9cc0e0f-1a57-44ae-861d-83a8e91e2d58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1118233669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_128.1118233669 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/38.kmac_test_vectors_shake_256.178867644
Short name T519
Test name
Test status
Simulation time 451974105310 ps
CPU time 5489.38 seconds
Started Feb 25 02:01:40 PM PST 24
Finished Feb 25 03:33:10 PM PST 24
Peak memory 565260 kb
Host smart-9f3d5e1e-2c22-4188-99ce-b843b64f9fab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=178867644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_256.178867644 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/39.kmac_alert_test.118900050
Short name T473
Test name
Test status
Simulation time 41045267 ps
CPU time 0.94 seconds
Started Feb 25 02:02:10 PM PST 24
Finished Feb 25 02:02:12 PM PST 24
Peak memory 218076 kb
Host smart-e685ca26-03be-4799-a9e2-72a7efc8a034
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118900050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.118900050 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/39.kmac_alert_test/latest


Test location /workspace/coverage/default/39.kmac_app.4162709662
Short name T439
Test name
Test status
Simulation time 599903746 ps
CPU time 38.35 seconds
Started Feb 25 02:02:04 PM PST 24
Finished Feb 25 02:02:43 PM PST 24
Peak memory 226928 kb
Host smart-d5376f84-b002-4278-840a-780b555a9e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162709662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.4162709662 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_app/latest


Test location /workspace/coverage/default/39.kmac_burst_write.917668976
Short name T1060
Test name
Test status
Simulation time 19243217878 ps
CPU time 892.16 seconds
Started Feb 25 02:02:01 PM PST 24
Finished Feb 25 02:16:54 PM PST 24
Peak memory 237336 kb
Host smart-6e0349d2-0e28-48fd-951a-26b71738f2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917668976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.917668976 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_burst_write/latest


Test location /workspace/coverage/default/39.kmac_entropy_refresh.3430844520
Short name T74
Test name
Test status
Simulation time 6580775145 ps
CPU time 278.52 seconds
Started Feb 25 02:02:08 PM PST 24
Finished Feb 25 02:06:49 PM PST 24
Peak memory 246332 kb
Host smart-2b5acc15-611d-4f9a-82ad-dd2ad8adab7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430844520 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.3430844520 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/39.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/39.kmac_error.1663228736
Short name T245
Test name
Test status
Simulation time 21566872514 ps
CPU time 172.44 seconds
Started Feb 25 02:02:03 PM PST 24
Finished Feb 25 02:04:55 PM PST 24
Peak memory 251204 kb
Host smart-eafc6910-e9d7-4285-abae-89d601c0711f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663228736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.1663228736 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_error/latest


Test location /workspace/coverage/default/39.kmac_key_error.3630611161
Short name T740
Test name
Test status
Simulation time 360968508 ps
CPU time 1.83 seconds
Started Feb 25 02:01:58 PM PST 24
Finished Feb 25 02:02:00 PM PST 24
Peak memory 218148 kb
Host smart-e3c9430c-3a89-4c35-9a8b-e921b6a18eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630611161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.3630611161 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_key_error/latest


Test location /workspace/coverage/default/39.kmac_lc_escalation.1844458819
Short name T84
Test name
Test status
Simulation time 45596114 ps
CPU time 1.45 seconds
Started Feb 25 02:02:09 PM PST 24
Finished Feb 25 02:02:11 PM PST 24
Peak memory 219312 kb
Host smart-b1f4bed0-0c82-488e-bdd1-adbadcf8960b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844458819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.1844458819 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/39.kmac_lc_escalation/latest


Test location /workspace/coverage/default/39.kmac_long_msg_and_output.3879421534
Short name T799
Test name
Test status
Simulation time 96130007217 ps
CPU time 2497.51 seconds
Started Feb 25 02:01:59 PM PST 24
Finished Feb 25 02:43:37 PM PST 24
Peak memory 428524 kb
Host smart-6f9e0860-665c-46a5-bd28-4dab5b047d84
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879421534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_a
nd_output.3879421534 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/39.kmac_sideload.868946097
Short name T338
Test name
Test status
Simulation time 1064924824 ps
CPU time 39.12 seconds
Started Feb 25 02:02:09 PM PST 24
Finished Feb 25 02:02:49 PM PST 24
Peak memory 233976 kb
Host smart-9e356b19-29c6-4053-bce4-d11f3c1fa7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868946097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.868946097 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_sideload/latest


Test location /workspace/coverage/default/39.kmac_smoke.4116839816
Short name T1072
Test name
Test status
Simulation time 1623730833 ps
CPU time 61.58 seconds
Started Feb 25 02:01:58 PM PST 24
Finished Feb 25 02:03:00 PM PST 24
Peak memory 226560 kb
Host smart-45daec36-c80a-4c46-9bf8-680692b99816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116839816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.4116839816 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_smoke/latest


Test location /workspace/coverage/default/39.kmac_stress_all.62727364
Short name T901
Test name
Test status
Simulation time 129667357608 ps
CPU time 916.14 seconds
Started Feb 25 02:02:10 PM PST 24
Finished Feb 25 02:17:27 PM PST 24
Peak memory 317756 kb
Host smart-3a2d2367-8b0d-4d7d-b92e-170a855a814c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=62727364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.62727364 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_stress_all/latest


Test location /workspace/coverage/default/39.kmac_test_vectors_kmac.1295221347
Short name T550
Test name
Test status
Simulation time 569205500 ps
CPU time 7.39 seconds
Started Feb 25 02:02:05 PM PST 24
Finished Feb 25 02:02:13 PM PST 24
Peak memory 219880 kb
Host smart-63f3b0f4-7260-414b-b809-c8b6e9330266
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295221347 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.kmac_test_vectors_kmac.1295221347 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/39.kmac_test_vectors_kmac_xof.3123144749
Short name T225
Test name
Test status
Simulation time 1279668012 ps
CPU time 5.43 seconds
Started Feb 25 02:02:03 PM PST 24
Finished Feb 25 02:02:08 PM PST 24
Peak memory 218388 kb
Host smart-f6beaaf3-4139-4232-81a5-fa85a0a9447f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123144749 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.kmac_test_vectors_kmac_xof.3123144749 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_224.2072263259
Short name T292
Test name
Test status
Simulation time 545131536346 ps
CPU time 2363.92 seconds
Started Feb 25 02:02:08 PM PST 24
Finished Feb 25 02:41:34 PM PST 24
Peak memory 401464 kb
Host smart-2ac53c6c-6a5a-4538-96e0-32cf1aadc8b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2072263259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_224.2072263259 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_256.4100205229
Short name T788
Test name
Test status
Simulation time 19818347164 ps
CPU time 1986.06 seconds
Started Feb 25 02:01:58 PM PST 24
Finished Feb 25 02:35:05 PM PST 24
Peak memory 387760 kb
Host smart-d3f251cd-aa4d-4e86-b01d-59f37d750fa8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4100205229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_256.4100205229 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_384.2546409274
Short name T326
Test name
Test status
Simulation time 18113926063 ps
CPU time 1781.28 seconds
Started Feb 25 02:02:00 PM PST 24
Finished Feb 25 02:31:41 PM PST 24
Peak memory 349144 kb
Host smart-b1f77eea-48d0-42ac-877a-36a1f2b1f601
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2546409274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_384.2546409274 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_512.2940082402
Short name T419
Test name
Test status
Simulation time 25204813075 ps
CPU time 1259.66 seconds
Started Feb 25 02:02:08 PM PST 24
Finished Feb 25 02:23:08 PM PST 24
Peak memory 300924 kb
Host smart-6cefd692-c933-4c3c-a554-a757fecb3b2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2940082402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_512.2940082402 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/39.kmac_test_vectors_shake_128.2298489095
Short name T900
Test name
Test status
Simulation time 4250049330157 ps
CPU time 6525.48 seconds
Started Feb 25 02:02:02 PM PST 24
Finished Feb 25 03:50:49 PM PST 24
Peak memory 646660 kb
Host smart-06e9510e-79ba-4904-abdd-572e3e5a9bd1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2298489095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_128.2298489095 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/39.kmac_test_vectors_shake_256.262081306
Short name T647
Test name
Test status
Simulation time 127551940233 ps
CPU time 4823.82 seconds
Started Feb 25 02:02:07 PM PST 24
Finished Feb 25 03:22:32 PM PST 24
Peak memory 584004 kb
Host smart-468d1b87-5680-4823-bb45-a058c6a26120
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=262081306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_256.262081306 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/4.kmac_alert_test.1681558898
Short name T952
Test name
Test status
Simulation time 51952905 ps
CPU time 0.88 seconds
Started Feb 25 01:55:41 PM PST 24
Finished Feb 25 01:55:42 PM PST 24
Peak memory 218316 kb
Host smart-3320504d-2dbc-4dc9-9971-4bbf95e032c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681558898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.1681558898 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_alert_test/latest


Test location /workspace/coverage/default/4.kmac_app.2656824737
Short name T423
Test name
Test status
Simulation time 5649670663 ps
CPU time 136.99 seconds
Started Feb 25 01:55:44 PM PST 24
Finished Feb 25 01:58:01 PM PST 24
Peak memory 235944 kb
Host smart-1a5c65ef-b84e-4ea9-9f8c-7bdcfd4f98a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656824737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.2656824737 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_app/latest


Test location /workspace/coverage/default/4.kmac_app_with_partial_data.334140234
Short name T888
Test name
Test status
Simulation time 21813056577 ps
CPU time 193.69 seconds
Started Feb 25 01:55:44 PM PST 24
Finished Feb 25 01:58:58 PM PST 24
Peak memory 240660 kb
Host smart-012c7b58-c18f-4c80-92e7-7697c34526c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334140234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.334140234 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/4.kmac_app_with_partial_data/latest


Test location /workspace/coverage/default/4.kmac_burst_write.808761375
Short name T830
Test name
Test status
Simulation time 124166802591 ps
CPU time 1159.63 seconds
Started Feb 25 01:55:40 PM PST 24
Finished Feb 25 02:15:00 PM PST 24
Peak memory 243136 kb
Host smart-92f6c359-46e6-4308-9ff7-5d628548a5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808761375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.808761375 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_burst_write/latest


Test location /workspace/coverage/default/4.kmac_edn_timeout_error.2434260341
Short name T871
Test name
Test status
Simulation time 55632220 ps
CPU time 1 seconds
Started Feb 25 01:55:42 PM PST 24
Finished Feb 25 01:55:43 PM PST 24
Peak memory 218156 kb
Host smart-8bac8ed6-641e-45a3-a069-fd1e6e6b4c4f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2434260341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.2434260341 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/4.kmac_entropy_mode_error.3388968658
Short name T339
Test name
Test status
Simulation time 283402442 ps
CPU time 0.99 seconds
Started Feb 25 01:55:41 PM PST 24
Finished Feb 25 01:55:42 PM PST 24
Peak memory 218148 kb
Host smart-0c5b685e-a6b0-499e-b171-d4e713dee20a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3388968658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.3388968658 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/4.kmac_entropy_ready_error.2786772699
Short name T489
Test name
Test status
Simulation time 4915732643 ps
CPU time 53.76 seconds
Started Feb 25 01:55:41 PM PST 24
Finished Feb 25 01:56:35 PM PST 24
Peak memory 220860 kb
Host smart-3d39ece8-fbc4-44f3-bc8a-85c5b5e3cb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786772699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.2786772699 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_ready_error/latest


Test location /workspace/coverage/default/4.kmac_entropy_refresh.2121529491
Short name T171
Test name
Test status
Simulation time 5746257887 ps
CPU time 132.03 seconds
Started Feb 25 01:55:45 PM PST 24
Finished Feb 25 01:57:57 PM PST 24
Peak memory 236968 kb
Host smart-83a63738-c67d-4b99-850d-77153e203320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121529491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.2121529491 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/4.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/4.kmac_error.1533403765
Short name T925
Test name
Test status
Simulation time 5229501140 ps
CPU time 363.02 seconds
Started Feb 25 01:55:51 PM PST 24
Finished Feb 25 02:01:55 PM PST 24
Peak memory 259440 kb
Host smart-4eda6872-41ba-4399-af64-276a480de230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533403765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.1533403765 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_error/latest


Test location /workspace/coverage/default/4.kmac_key_error.2454610117
Short name T963
Test name
Test status
Simulation time 4201631958 ps
CPU time 2.94 seconds
Started Feb 25 01:55:43 PM PST 24
Finished Feb 25 01:55:46 PM PST 24
Peak memory 218444 kb
Host smart-e4933e46-08ed-4322-b68b-949c575509fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454610117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.2454610117 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_key_error/latest


Test location /workspace/coverage/default/4.kmac_lc_escalation.930808109
Short name T358
Test name
Test status
Simulation time 50614377 ps
CPU time 1.26 seconds
Started Feb 25 01:55:39 PM PST 24
Finished Feb 25 01:55:41 PM PST 24
Peak memory 219440 kb
Host smart-8f6e2563-47ee-4bcb-b1f7-946802d7b9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930808109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.930808109 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_lc_escalation/latest


Test location /workspace/coverage/default/4.kmac_long_msg_and_output.274632600
Short name T885
Test name
Test status
Simulation time 335254875677 ps
CPU time 3100.82 seconds
Started Feb 25 01:55:43 PM PST 24
Finished Feb 25 02:47:24 PM PST 24
Peak memory 460272 kb
Host smart-dd2ff5c9-95be-47e5-a519-541d3366f6b8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274632600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_and
_output.274632600 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/4.kmac_mubi.4264937739
Short name T804
Test name
Test status
Simulation time 4225983226 ps
CPU time 109.56 seconds
Started Feb 25 01:55:52 PM PST 24
Finished Feb 25 01:57:42 PM PST 24
Peak memory 236652 kb
Host smart-ece5e006-31cf-4558-8392-3d9c89a9b352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264937739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.4264937739 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mubi/latest


Test location /workspace/coverage/default/4.kmac_sec_cm.2691947048
Short name T7
Test name
Test status
Simulation time 30461941461 ps
CPU time 105.94 seconds
Started Feb 25 01:55:40 PM PST 24
Finished Feb 25 01:57:26 PM PST 24
Peak memory 310988 kb
Host smart-fe5b0962-281f-4112-8485-77db0a788e50
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691947048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.2691947048 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/4.kmac_sec_cm/latest


Test location /workspace/coverage/default/4.kmac_sideload.2747492454
Short name T651
Test name
Test status
Simulation time 32166460715 ps
CPU time 290.3 seconds
Started Feb 25 01:55:41 PM PST 24
Finished Feb 25 02:00:32 PM PST 24
Peak memory 245344 kb
Host smart-445489f0-9615-4d16-b094-9af820984bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747492454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.2747492454 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_sideload/latest


Test location /workspace/coverage/default/4.kmac_smoke.2265172251
Short name T764
Test name
Test status
Simulation time 619176818 ps
CPU time 5.02 seconds
Started Feb 25 01:55:42 PM PST 24
Finished Feb 25 01:55:47 PM PST 24
Peak memory 218644 kb
Host smart-62b80c7c-eb8f-459b-bdf6-75486ee3fa29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265172251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.2265172251 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_smoke/latest


Test location /workspace/coverage/default/4.kmac_stress_all.567582233
Short name T936
Test name
Test status
Simulation time 18237136226 ps
CPU time 1504.37 seconds
Started Feb 25 01:55:40 PM PST 24
Finished Feb 25 02:20:45 PM PST 24
Peak memory 390688 kb
Host smart-fec148f2-187a-4a6c-96be-a67334578261
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=567582233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.567582233 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_stress_all/latest


Test location /workspace/coverage/default/4.kmac_stress_all_with_rand_reset.1790344269
Short name T54
Test name
Test status
Simulation time 151129542431 ps
CPU time 2775.35 seconds
Started Feb 25 01:55:39 PM PST 24
Finished Feb 25 02:41:55 PM PST 24
Peak memory 390764 kb
Host smart-d6e927ee-f8fa-4f6e-b5e5-7744720f4c60
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1790344269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all_with_rand_reset.1790344269 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/4.kmac_test_vectors_kmac.2231059336
Short name T652
Test name
Test status
Simulation time 487419101 ps
CPU time 6.55 seconds
Started Feb 25 01:55:42 PM PST 24
Finished Feb 25 01:55:49 PM PST 24
Peak memory 218472 kb
Host smart-bf86d885-5388-4b75-8ab4-0491ae2f7f76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231059336 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.kmac_test_vectors_kmac.2231059336 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/4.kmac_test_vectors_kmac_xof.2145076333
Short name T580
Test name
Test status
Simulation time 967527520 ps
CPU time 6.2 seconds
Started Feb 25 01:55:40 PM PST 24
Finished Feb 25 01:55:47 PM PST 24
Peak memory 219764 kb
Host smart-8747aac4-b1a8-4e06-a78a-9d25a3fab197
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145076333 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.kmac_test_vectors_kmac_xof.2145076333 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_224.3779274620
Short name T932
Test name
Test status
Simulation time 718731883488 ps
CPU time 2268.95 seconds
Started Feb 25 01:55:42 PM PST 24
Finished Feb 25 02:33:31 PM PST 24
Peak memory 394044 kb
Host smart-500c955d-a9e0-4f58-a69c-d02ce37600eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3779274620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.3779274620 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_256.1744371195
Short name T1062
Test name
Test status
Simulation time 258177229462 ps
CPU time 2256.23 seconds
Started Feb 25 01:55:44 PM PST 24
Finished Feb 25 02:33:20 PM PST 24
Peak memory 389688 kb
Host smart-fe618fa9-db0b-4d4a-8078-3090dc98533d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1744371195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.1744371195 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_384.3905798146
Short name T189
Test name
Test status
Simulation time 97581808468 ps
CPU time 1838.68 seconds
Started Feb 25 01:55:39 PM PST 24
Finished Feb 25 02:26:18 PM PST 24
Peak memory 343344 kb
Host smart-7792c8d5-9495-4fff-bd89-f7e9d2c57d06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3905798146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.3905798146 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_512.240702531
Short name T889
Test name
Test status
Simulation time 96520320872 ps
CPU time 1345.37 seconds
Started Feb 25 01:55:44 PM PST 24
Finished Feb 25 02:18:10 PM PST 24
Peak memory 297680 kb
Host smart-60f704c8-8b80-4c0d-a3dd-b1f4630aedf6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=240702531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.240702531 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/4.kmac_test_vectors_shake_128.1129646141
Short name T970
Test name
Test status
Simulation time 60822956753 ps
CPU time 5590.76 seconds
Started Feb 25 01:55:39 PM PST 24
Finished Feb 25 03:28:51 PM PST 24
Peak memory 645384 kb
Host smart-901eee9e-078d-4a4d-9b97-59c7c2218b20
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1129646141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.1129646141 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/4.kmac_test_vectors_shake_256.1918721902
Short name T371
Test name
Test status
Simulation time 54268542096 ps
CPU time 4196.87 seconds
Started Feb 25 01:55:46 PM PST 24
Finished Feb 25 03:05:43 PM PST 24
Peak memory 576372 kb
Host smart-a92ebc62-e48d-4f27-a2d4-188a9921247b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1918721902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.1918721902 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/40.kmac_alert_test.2563197371
Short name T1042
Test name
Test status
Simulation time 33224324 ps
CPU time 0.81 seconds
Started Feb 25 02:02:35 PM PST 24
Finished Feb 25 02:02:37 PM PST 24
Peak memory 219232 kb
Host smart-cc942b17-55d1-47cb-9f63-c36fb7ed4d97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563197371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.2563197371 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_alert_test/latest


Test location /workspace/coverage/default/40.kmac_app.715415011
Short name T396
Test name
Test status
Simulation time 6254323473 ps
CPU time 134.06 seconds
Started Feb 25 02:02:21 PM PST 24
Finished Feb 25 02:04:35 PM PST 24
Peak memory 236368 kb
Host smart-5e3c62f4-9332-4605-87f8-fbb8ca92ef2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715415011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.715415011 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_app/latest


Test location /workspace/coverage/default/40.kmac_burst_write.3852518392
Short name T715
Test name
Test status
Simulation time 1775082583 ps
CPU time 6.52 seconds
Started Feb 25 02:02:10 PM PST 24
Finished Feb 25 02:02:17 PM PST 24
Peak memory 221540 kb
Host smart-26102c84-86fc-4b70-9ed9-291e3ca9de50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852518392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.3852518392 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_burst_write/latest


Test location /workspace/coverage/default/40.kmac_entropy_refresh.684508960
Short name T928
Test name
Test status
Simulation time 54941368279 ps
CPU time 345.29 seconds
Started Feb 25 02:02:18 PM PST 24
Finished Feb 25 02:08:04 PM PST 24
Peak memory 248980 kb
Host smart-3cb769af-6578-445b-ac48-56b00c35afd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684508960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.684508960 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/40.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/40.kmac_error.3799895901
Short name T73
Test name
Test status
Simulation time 3037653680 ps
CPU time 101.87 seconds
Started Feb 25 02:02:17 PM PST 24
Finished Feb 25 02:03:59 PM PST 24
Peak memory 241536 kb
Host smart-d87dfdbe-81c0-4076-b332-4cfc1c152cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799895901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.3799895901 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_error/latest


Test location /workspace/coverage/default/40.kmac_key_error.3286661518
Short name T348
Test name
Test status
Simulation time 309186769 ps
CPU time 2.28 seconds
Started Feb 25 02:02:37 PM PST 24
Finished Feb 25 02:02:40 PM PST 24
Peak memory 218256 kb
Host smart-8b59ddf0-adfc-4745-8497-59c8498a8c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286661518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.3286661518 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_key_error/latest


Test location /workspace/coverage/default/40.kmac_lc_escalation.3223627824
Short name T48
Test name
Test status
Simulation time 583194303 ps
CPU time 14.52 seconds
Started Feb 25 02:02:34 PM PST 24
Finished Feb 25 02:02:49 PM PST 24
Peak memory 234752 kb
Host smart-05960bf8-a4e0-422d-a490-0c65f3acd820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223627824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.3223627824 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/40.kmac_lc_escalation/latest


Test location /workspace/coverage/default/40.kmac_long_msg_and_output.812481687
Short name T1000
Test name
Test status
Simulation time 36841569930 ps
CPU time 1370.23 seconds
Started Feb 25 02:02:11 PM PST 24
Finished Feb 25 02:25:02 PM PST 24
Peak memory 332204 kb
Host smart-17c39bdf-bd93-420a-89ce-b37268ae4aef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812481687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_an
d_output.812481687 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/40.kmac_sideload.3207331623
Short name T321
Test name
Test status
Simulation time 67882597938 ps
CPU time 504.27 seconds
Started Feb 25 02:02:11 PM PST 24
Finished Feb 25 02:10:35 PM PST 24
Peak memory 257464 kb
Host smart-4a2b93ac-8aa9-4471-a3ac-bda2e62e8c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207331623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.3207331623 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_sideload/latest


Test location /workspace/coverage/default/40.kmac_smoke.3640908934
Short name T664
Test name
Test status
Simulation time 8689226971 ps
CPU time 79 seconds
Started Feb 25 02:02:09 PM PST 24
Finished Feb 25 02:03:29 PM PST 24
Peak memory 224392 kb
Host smart-12461bfd-7690-49f1-af64-8073d2bdef65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640908934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.3640908934 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_smoke/latest


Test location /workspace/coverage/default/40.kmac_stress_all.1703612304
Short name T523
Test name
Test status
Simulation time 14058051528 ps
CPU time 408.49 seconds
Started Feb 25 02:02:35 PM PST 24
Finished Feb 25 02:09:24 PM PST 24
Peak memory 283932 kb
Host smart-45d76181-ecad-44dd-86bf-60d446c2db71
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1703612304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.1703612304 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_stress_all/latest


Test location /workspace/coverage/default/40.kmac_test_vectors_kmac.3779514964
Short name T451
Test name
Test status
Simulation time 214310490 ps
CPU time 6.27 seconds
Started Feb 25 02:02:20 PM PST 24
Finished Feb 25 02:02:27 PM PST 24
Peak memory 219840 kb
Host smart-92f37701-56d3-483b-bce9-34d27a39e48b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779514964 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.kmac_test_vectors_kmac.3779514964 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/40.kmac_test_vectors_kmac_xof.657656298
Short name T623
Test name
Test status
Simulation time 281356105 ps
CPU time 7.34 seconds
Started Feb 25 02:02:18 PM PST 24
Finished Feb 25 02:02:25 PM PST 24
Peak memory 219612 kb
Host smart-b4a62881-feab-48e1-a463-0a3241301605
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657656298 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.kmac_test_vectors_kmac_xof.657656298 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_224.2241301194
Short name T418
Test name
Test status
Simulation time 130632236206 ps
CPU time 2586.53 seconds
Started Feb 25 02:02:17 PM PST 24
Finished Feb 25 02:45:24 PM PST 24
Peak memory 389956 kb
Host smart-62cd43a2-ff6b-4104-8c9c-5588e702459e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2241301194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_224.2241301194 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_256.2245995406
Short name T1028
Test name
Test status
Simulation time 19330826862 ps
CPU time 1901.96 seconds
Started Feb 25 02:02:19 PM PST 24
Finished Feb 25 02:34:01 PM PST 24
Peak memory 379252 kb
Host smart-14c34d08-95ce-455b-9442-2b54cff8ec77
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2245995406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_256.2245995406 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_384.1320191638
Short name T341
Test name
Test status
Simulation time 480792419130 ps
CPU time 1653.36 seconds
Started Feb 25 02:02:21 PM PST 24
Finished Feb 25 02:29:54 PM PST 24
Peak memory 346044 kb
Host smart-993ae64f-6e54-42ed-a79f-d4995bc96594
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1320191638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_384.1320191638 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_512.183023526
Short name T1065
Test name
Test status
Simulation time 14335972710 ps
CPU time 1002.17 seconds
Started Feb 25 02:02:17 PM PST 24
Finished Feb 25 02:19:00 PM PST 24
Peak memory 301412 kb
Host smart-30d18789-b78c-410f-94c8-de9e9a0e276b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=183023526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_512.183023526 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/40.kmac_test_vectors_shake_128.3187084367
Short name T491
Test name
Test status
Simulation time 731380784633 ps
CPU time 5741.96 seconds
Started Feb 25 02:02:19 PM PST 24
Finished Feb 25 03:38:02 PM PST 24
Peak memory 644948 kb
Host smart-27e39914-a960-4b8a-95cf-07b78a7e4790
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3187084367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_128.3187084367 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/40.kmac_test_vectors_shake_256.3380078348
Short name T996
Test name
Test status
Simulation time 881570042017 ps
CPU time 5501.09 seconds
Started Feb 25 02:02:16 PM PST 24
Finished Feb 25 03:33:58 PM PST 24
Peak memory 573232 kb
Host smart-1f5700ed-47cf-47b7-b758-047fe77b0cf2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3380078348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_256.3380078348 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/41.kmac_alert_test.725407187
Short name T514
Test name
Test status
Simulation time 45861550 ps
CPU time 0.84 seconds
Started Feb 25 02:02:53 PM PST 24
Finished Feb 25 02:02:54 PM PST 24
Peak memory 218112 kb
Host smart-37482bf9-38d8-4a1d-b2dc-662081b02bbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725407187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.725407187 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/41.kmac_alert_test/latest


Test location /workspace/coverage/default/41.kmac_app.2360703296
Short name T994
Test name
Test status
Simulation time 7757795451 ps
CPU time 179.92 seconds
Started Feb 25 02:02:54 PM PST 24
Finished Feb 25 02:05:54 PM PST 24
Peak memory 241140 kb
Host smart-d1921aa2-6878-4072-923b-2d75a758b906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360703296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.2360703296 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_app/latest


Test location /workspace/coverage/default/41.kmac_burst_write.1656924347
Short name T59
Test name
Test status
Simulation time 28052367028 ps
CPU time 644.67 seconds
Started Feb 25 02:02:36 PM PST 24
Finished Feb 25 02:13:22 PM PST 24
Peak memory 233788 kb
Host smart-86d9ebe9-09f0-4c7d-b08d-ee658c990ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656924347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.1656924347 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_burst_write/latest


Test location /workspace/coverage/default/41.kmac_entropy_refresh.2615994642
Short name T78
Test name
Test status
Simulation time 11805943990 ps
CPU time 297.31 seconds
Started Feb 25 02:02:49 PM PST 24
Finished Feb 25 02:07:46 PM PST 24
Peak memory 246560 kb
Host smart-f920f50e-8334-433c-8b37-0258f8aee226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615994642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.2615994642 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/41.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/41.kmac_error.2412218353
Short name T457
Test name
Test status
Simulation time 21573833323 ps
CPU time 361.7 seconds
Started Feb 25 02:02:48 PM PST 24
Finished Feb 25 02:08:50 PM PST 24
Peak memory 266080 kb
Host smart-645305b5-16c7-4f5d-a8d3-6a65de4fcc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412218353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.2412218353 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_error/latest


Test location /workspace/coverage/default/41.kmac_key_error.2199641896
Short name T458
Test name
Test status
Simulation time 2010105474 ps
CPU time 4.03 seconds
Started Feb 25 02:02:53 PM PST 24
Finished Feb 25 02:02:57 PM PST 24
Peak memory 218328 kb
Host smart-7fb64a04-039f-485b-be41-1876cfdd9af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199641896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.2199641896 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_key_error/latest


Test location /workspace/coverage/default/41.kmac_lc_escalation.692662344
Short name T1008
Test name
Test status
Simulation time 186289464 ps
CPU time 1.42 seconds
Started Feb 25 02:02:52 PM PST 24
Finished Feb 25 02:02:54 PM PST 24
Peak memory 219344 kb
Host smart-c32a8009-d068-4d7d-91f8-041b3ad3fb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692662344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.692662344 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/41.kmac_lc_escalation/latest


Test location /workspace/coverage/default/41.kmac_long_msg_and_output.2245249687
Short name T878
Test name
Test status
Simulation time 44219773414 ps
CPU time 1613.34 seconds
Started Feb 25 02:02:36 PM PST 24
Finished Feb 25 02:29:31 PM PST 24
Peak memory 350192 kb
Host smart-51a6222b-6be5-4635-a4dc-0b3b6a421ead
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245249687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_a
nd_output.2245249687 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/41.kmac_sideload.3271167855
Short name T906
Test name
Test status
Simulation time 70989372833 ps
CPU time 397.31 seconds
Started Feb 25 02:02:36 PM PST 24
Finished Feb 25 02:09:14 PM PST 24
Peak memory 250768 kb
Host smart-6f8a7cd9-417d-42c2-8a86-6b058d1bbc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271167855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.3271167855 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_sideload/latest


Test location /workspace/coverage/default/41.kmac_smoke.319755105
Short name T188
Test name
Test status
Simulation time 12496460737 ps
CPU time 88.5 seconds
Started Feb 25 02:02:36 PM PST 24
Finished Feb 25 02:04:05 PM PST 24
Peak memory 226664 kb
Host smart-86898c05-acdb-4884-ab32-801219617e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319755105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.319755105 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_smoke/latest


Test location /workspace/coverage/default/41.kmac_stress_all.192970881
Short name T1053
Test name
Test status
Simulation time 131040823164 ps
CPU time 1761.84 seconds
Started Feb 25 02:02:51 PM PST 24
Finished Feb 25 02:32:14 PM PST 24
Peak memory 403420 kb
Host smart-b573f8d2-de5f-427a-985b-be980e7957f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=192970881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.192970881 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_stress_all/latest


Test location /workspace/coverage/default/41.kmac_test_vectors_kmac.2653798017
Short name T624
Test name
Test status
Simulation time 1200981176 ps
CPU time 7.19 seconds
Started Feb 25 02:02:53 PM PST 24
Finished Feb 25 02:03:00 PM PST 24
Peak memory 219668 kb
Host smart-99505da2-b8a3-4d3f-9eaf-9d9793a17285
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653798017 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.kmac_test_vectors_kmac.2653798017 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/41.kmac_test_vectors_kmac_xof.1887455097
Short name T384
Test name
Test status
Simulation time 197924002 ps
CPU time 6.72 seconds
Started Feb 25 02:02:47 PM PST 24
Finished Feb 25 02:02:54 PM PST 24
Peak memory 218480 kb
Host smart-067258f4-6862-4b4c-aec4-8826fc0c2e9c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887455097 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.kmac_test_vectors_kmac_xof.1887455097 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_224.2615979337
Short name T780
Test name
Test status
Simulation time 79555951449 ps
CPU time 2398.96 seconds
Started Feb 25 02:02:53 PM PST 24
Finished Feb 25 02:42:52 PM PST 24
Peak memory 399668 kb
Host smart-146b194a-a545-4a2e-ba0e-11d1c8ae3e2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2615979337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_224.2615979337 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_256.3927169221
Short name T247
Test name
Test status
Simulation time 124877100921 ps
CPU time 2223.76 seconds
Started Feb 25 02:02:52 PM PST 24
Finished Feb 25 02:39:56 PM PST 24
Peak memory 390272 kb
Host smart-f14e7844-4479-4ffa-8b9f-63771fce1df0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3927169221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_256.3927169221 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_384.2159544165
Short name T943
Test name
Test status
Simulation time 124431433381 ps
CPU time 1893.35 seconds
Started Feb 25 02:02:52 PM PST 24
Finished Feb 25 02:34:26 PM PST 24
Peak memory 340864 kb
Host smart-770f9910-f8b2-4d69-9ed3-09d54ffd2c6c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2159544165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_384.2159544165 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_512.1275469909
Short name T192
Test name
Test status
Simulation time 21716296535 ps
CPU time 1309.78 seconds
Started Feb 25 02:02:51 PM PST 24
Finished Feb 25 02:24:41 PM PST 24
Peak memory 298368 kb
Host smart-472ebc85-e825-4596-be2e-ddc328f3ab4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1275469909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_512.1275469909 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/41.kmac_test_vectors_shake_128.4228268495
Short name T554
Test name
Test status
Simulation time 139258663460 ps
CPU time 5273.53 seconds
Started Feb 25 02:02:47 PM PST 24
Finished Feb 25 03:30:41 PM PST 24
Peak memory 638848 kb
Host smart-3944ebf8-e608-474a-8e8b-b2b587a11780
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4228268495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_128.4228268495 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/41.kmac_test_vectors_shake_256.318758799
Short name T1003
Test name
Test status
Simulation time 260763663318 ps
CPU time 4470.69 seconds
Started Feb 25 02:02:52 PM PST 24
Finished Feb 25 03:17:23 PM PST 24
Peak memory 566564 kb
Host smart-e568fd27-8fcc-463a-8d60-fa972487a808
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=318758799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_256.318758799 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/42.kmac_alert_test.2160764517
Short name T714
Test name
Test status
Simulation time 45517348 ps
CPU time 0.87 seconds
Started Feb 25 02:03:11 PM PST 24
Finished Feb 25 02:03:12 PM PST 24
Peak memory 218088 kb
Host smart-cd727022-1f97-424f-b434-c5e263ac6a75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160764517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.2160764517 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_alert_test/latest


Test location /workspace/coverage/default/42.kmac_app.106679921
Short name T1019
Test name
Test status
Simulation time 103662091960 ps
CPU time 264.61 seconds
Started Feb 25 02:03:00 PM PST 24
Finished Feb 25 02:07:25 PM PST 24
Peak memory 245144 kb
Host smart-81928d38-bad0-44ec-8408-1397330abd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106679921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.106679921 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_app/latest


Test location /workspace/coverage/default/42.kmac_burst_write.2991340878
Short name T475
Test name
Test status
Simulation time 33678856478 ps
CPU time 1305.05 seconds
Started Feb 25 02:03:00 PM PST 24
Finished Feb 25 02:24:45 PM PST 24
Peak memory 239848 kb
Host smart-ab02817a-8df2-41b2-8a6c-f4332abf380e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991340878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.2991340878 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_burst_write/latest


Test location /workspace/coverage/default/42.kmac_entropy_refresh.2386421421
Short name T1038
Test name
Test status
Simulation time 14547437359 ps
CPU time 154.95 seconds
Started Feb 25 02:03:02 PM PST 24
Finished Feb 25 02:05:37 PM PST 24
Peak memory 243052 kb
Host smart-37e27ca0-4949-48c5-9c74-43bf89ea9849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386421421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.2386421421 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/42.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/42.kmac_error.2389271767
Short name T713
Test name
Test status
Simulation time 6025833077 ps
CPU time 498.25 seconds
Started Feb 25 02:03:11 PM PST 24
Finished Feb 25 02:11:29 PM PST 24
Peak memory 275836 kb
Host smart-5efa78a9-bd95-45e5-8a2c-3884f32a3b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389271767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.2389271767 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_error/latest


Test location /workspace/coverage/default/42.kmac_key_error.4099536559
Short name T529
Test name
Test status
Simulation time 3766675110 ps
CPU time 5.9 seconds
Started Feb 25 02:03:11 PM PST 24
Finished Feb 25 02:03:17 PM PST 24
Peak memory 218288 kb
Host smart-d19d175d-6599-4adf-92ce-4d3dd6daa208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099536559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.4099536559 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_key_error/latest


Test location /workspace/coverage/default/42.kmac_lc_escalation.2620772633
Short name T620
Test name
Test status
Simulation time 67526455 ps
CPU time 1.35 seconds
Started Feb 25 02:03:12 PM PST 24
Finished Feb 25 02:03:13 PM PST 24
Peak memory 219516 kb
Host smart-eee0d0b8-14db-4379-b7c9-a8e417d47bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620772633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.2620772633 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/42.kmac_lc_escalation/latest


Test location /workspace/coverage/default/42.kmac_long_msg_and_output.3885622804
Short name T676
Test name
Test status
Simulation time 28938788441 ps
CPU time 3184.19 seconds
Started Feb 25 02:02:51 PM PST 24
Finished Feb 25 02:55:56 PM PST 24
Peak memory 487580 kb
Host smart-5403142e-0a72-4bea-a4e2-1a07e7902799
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885622804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_a
nd_output.3885622804 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/42.kmac_sideload.342260489
Short name T706
Test name
Test status
Simulation time 6106159249 ps
CPU time 243.24 seconds
Started Feb 25 02:02:53 PM PST 24
Finished Feb 25 02:06:57 PM PST 24
Peak memory 245716 kb
Host smart-b2a5ddd5-8768-4d4d-9bda-215eb5620e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342260489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.342260489 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_sideload/latest


Test location /workspace/coverage/default/42.kmac_smoke.1097392801
Short name T461
Test name
Test status
Simulation time 10458782510 ps
CPU time 67.06 seconds
Started Feb 25 02:02:53 PM PST 24
Finished Feb 25 02:04:00 PM PST 24
Peak memory 220760 kb
Host smart-5078d91f-6d93-4ecb-a5ec-63efbc8d2cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097392801 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.1097392801 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_smoke/latest


Test location /workspace/coverage/default/42.kmac_stress_all.1199354143
Short name T441
Test name
Test status
Simulation time 17429602399 ps
CPU time 927.74 seconds
Started Feb 25 02:03:13 PM PST 24
Finished Feb 25 02:18:41 PM PST 24
Peak memory 322160 kb
Host smart-0e4ee38a-7b18-4138-869c-0430f0607a75
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1199354143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.1199354143 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_stress_all/latest


Test location /workspace/coverage/default/42.kmac_test_vectors_kmac.839537328
Short name T787
Test name
Test status
Simulation time 182672687 ps
CPU time 6.2 seconds
Started Feb 25 02:03:00 PM PST 24
Finished Feb 25 02:03:07 PM PST 24
Peak memory 219956 kb
Host smart-2bbbdc73-e4cb-41d9-96f1-d38225b1b636
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839537328 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.kmac_test_vectors_kmac.839537328 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/42.kmac_test_vectors_kmac_xof.1753393665
Short name T511
Test name
Test status
Simulation time 192557460 ps
CPU time 7.23 seconds
Started Feb 25 02:03:03 PM PST 24
Finished Feb 25 02:03:10 PM PST 24
Peak memory 219672 kb
Host smart-a0e0977a-37c4-45e1-a292-9a399115ed18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753393665 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.kmac_test_vectors_kmac_xof.1753393665 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_224.57987463
Short name T605
Test name
Test status
Simulation time 71536806408 ps
CPU time 2414.1 seconds
Started Feb 25 02:03:00 PM PST 24
Finished Feb 25 02:43:15 PM PST 24
Peak memory 395188 kb
Host smart-4b87f4e5-162f-4c49-bc78-91d6326ac184
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=57987463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_224.57987463 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_256.3936227672
Short name T485
Test name
Test status
Simulation time 185806666494 ps
CPU time 2323.43 seconds
Started Feb 25 02:03:00 PM PST 24
Finished Feb 25 02:41:44 PM PST 24
Peak memory 385456 kb
Host smart-faed034a-1af1-4ea2-b5fb-d3b19eeb8aab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3936227672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_256.3936227672 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_384.2653155420
Short name T191
Test name
Test status
Simulation time 76322471509 ps
CPU time 1592.21 seconds
Started Feb 25 02:03:00 PM PST 24
Finished Feb 25 02:29:33 PM PST 24
Peak memory 332360 kb
Host smart-b50bb1ca-63cd-4c0b-80a2-ef5a4b393bb5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2653155420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_384.2653155420 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_512.3363923202
Short name T957
Test name
Test status
Simulation time 11172103459 ps
CPU time 1187.12 seconds
Started Feb 25 02:03:03 PM PST 24
Finished Feb 25 02:22:51 PM PST 24
Peak memory 303120 kb
Host smart-7aeed610-6326-43e0-9408-5a0113a1149c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3363923202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_512.3363923202 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/42.kmac_test_vectors_shake_128.398924075
Short name T920
Test name
Test status
Simulation time 215260517315 ps
CPU time 5248.08 seconds
Started Feb 25 02:03:01 PM PST 24
Finished Feb 25 03:30:29 PM PST 24
Peak memory 661964 kb
Host smart-e5b65646-8214-49f4-b930-bf43e808f9ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=398924075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_128.398924075 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/42.kmac_test_vectors_shake_256.2934855043
Short name T898
Test name
Test status
Simulation time 1041461929062 ps
CPU time 5913.98 seconds
Started Feb 25 02:03:01 PM PST 24
Finished Feb 25 03:41:36 PM PST 24
Peak memory 575584 kb
Host smart-eb49ced2-10f2-4a20-9b75-3e2f0e73d50c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2934855043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_256.2934855043 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/43.kmac_alert_test.2408192354
Short name T800
Test name
Test status
Simulation time 245062898 ps
CPU time 0.86 seconds
Started Feb 25 02:03:32 PM PST 24
Finished Feb 25 02:03:33 PM PST 24
Peak memory 219252 kb
Host smart-81e63901-ecea-461b-8907-7af7a58cf76d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408192354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.2408192354 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_alert_test/latest


Test location /workspace/coverage/default/43.kmac_app.2058038448
Short name T921
Test name
Test status
Simulation time 15861144547 ps
CPU time 247.73 seconds
Started Feb 25 02:03:31 PM PST 24
Finished Feb 25 02:07:39 PM PST 24
Peak memory 244824 kb
Host smart-1ae4a88c-2ae7-4f31-b1f4-da30015a4730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058038448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.2058038448 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_app/latest


Test location /workspace/coverage/default/43.kmac_burst_write.2943109274
Short name T547
Test name
Test status
Simulation time 12189539932 ps
CPU time 293.95 seconds
Started Feb 25 02:03:11 PM PST 24
Finished Feb 25 02:08:05 PM PST 24
Peak memory 230352 kb
Host smart-0f852562-0733-4a37-866b-7ab9c1cca586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943109274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.2943109274 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_burst_write/latest


Test location /workspace/coverage/default/43.kmac_entropy_refresh.3198036936
Short name T319
Test name
Test status
Simulation time 958847333 ps
CPU time 36.43 seconds
Started Feb 25 02:03:33 PM PST 24
Finished Feb 25 02:04:09 PM PST 24
Peak memory 226824 kb
Host smart-036f8527-4d78-4828-be92-62ef8db30b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198036936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.3198036936 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/43.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/43.kmac_error.3040377431
Short name T47
Test name
Test status
Simulation time 10757199825 ps
CPU time 466.2 seconds
Started Feb 25 02:03:31 PM PST 24
Finished Feb 25 02:11:18 PM PST 24
Peak memory 259068 kb
Host smart-4f77b77e-c94b-44b5-b091-4321534bafeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040377431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.3040377431 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_error/latest


Test location /workspace/coverage/default/43.kmac_key_error.1737763939
Short name T969
Test name
Test status
Simulation time 609224803 ps
CPU time 3.92 seconds
Started Feb 25 02:03:33 PM PST 24
Finished Feb 25 02:03:37 PM PST 24
Peak memory 218224 kb
Host smart-fa303d18-ff27-4c8f-ae6f-24bbeb3c2814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737763939 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.1737763939 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_key_error/latest


Test location /workspace/coverage/default/43.kmac_lc_escalation.3726450225
Short name T688
Test name
Test status
Simulation time 41200055 ps
CPU time 1.21 seconds
Started Feb 25 02:03:32 PM PST 24
Finished Feb 25 02:03:33 PM PST 24
Peak memory 219404 kb
Host smart-c105ca39-5ffc-4720-816d-ee58a7bcdbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726450225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.3726450225 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/43.kmac_lc_escalation/latest


Test location /workspace/coverage/default/43.kmac_long_msg_and_output.423481664
Short name T531
Test name
Test status
Simulation time 25410033210 ps
CPU time 173.75 seconds
Started Feb 25 02:03:11 PM PST 24
Finished Feb 25 02:06:05 PM PST 24
Peak memory 241860 kb
Host smart-e9b90d4a-d7aa-429f-98fb-85525a69e030
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423481664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_an
d_output.423481664 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/43.kmac_sideload.4114531208
Short name T759
Test name
Test status
Simulation time 4835576352 ps
CPU time 466.79 seconds
Started Feb 25 02:03:12 PM PST 24
Finished Feb 25 02:10:59 PM PST 24
Peak memory 253560 kb
Host smart-aa2a963f-4c8f-47a6-963d-74e59b9d1155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114531208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.4114531208 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_sideload/latest


Test location /workspace/coverage/default/43.kmac_smoke.2416548020
Short name T332
Test name
Test status
Simulation time 11565263624 ps
CPU time 96.16 seconds
Started Feb 25 02:03:11 PM PST 24
Finished Feb 25 02:04:47 PM PST 24
Peak memory 226688 kb
Host smart-64d97edb-327d-485b-bd34-296e81c44d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416548020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.2416548020 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_smoke/latest


Test location /workspace/coverage/default/43.kmac_stress_all_with_rand_reset.193453282
Short name T125
Test name
Test status
Simulation time 71108699625 ps
CPU time 617.43 seconds
Started Feb 25 02:03:31 PM PST 24
Finished Feb 25 02:13:49 PM PST 24
Peak memory 292736 kb
Host smart-558e4b38-5aa5-45a8-9166-3f554806e0c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=193453282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all_with_rand_reset.193453282 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/43.kmac_test_vectors_kmac.295478703
Short name T438
Test name
Test status
Simulation time 1461532332 ps
CPU time 6.28 seconds
Started Feb 25 02:03:32 PM PST 24
Finished Feb 25 02:03:39 PM PST 24
Peak memory 219636 kb
Host smart-371b9d5f-d645-4c65-ad6a-49d11ba269e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295478703 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.kmac_test_vectors_kmac.295478703 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/43.kmac_test_vectors_kmac_xof.1522715178
Short name T382
Test name
Test status
Simulation time 3719275510 ps
CPU time 7.02 seconds
Started Feb 25 02:03:33 PM PST 24
Finished Feb 25 02:03:40 PM PST 24
Peak memory 218356 kb
Host smart-4c5736b8-5bcc-4e84-aea8-3056f3be7560
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522715178 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.kmac_test_vectors_kmac_xof.1522715178 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_224.104199313
Short name T342
Test name
Test status
Simulation time 20279979866 ps
CPU time 2062.25 seconds
Started Feb 25 02:03:31 PM PST 24
Finished Feb 25 02:37:53 PM PST 24
Peak memory 396068 kb
Host smart-2f430d04-d56f-4a3d-bdf0-449c5652af35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=104199313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_224.104199313 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_256.3692664257
Short name T682
Test name
Test status
Simulation time 93116253730 ps
CPU time 2258.83 seconds
Started Feb 25 02:03:31 PM PST 24
Finished Feb 25 02:41:10 PM PST 24
Peak memory 390552 kb
Host smart-75d0ae3c-2578-4f7d-8de7-4088d9c7c225
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3692664257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_256.3692664257 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_384.4118185671
Short name T629
Test name
Test status
Simulation time 259813622778 ps
CPU time 1832.56 seconds
Started Feb 25 02:03:31 PM PST 24
Finished Feb 25 02:34:04 PM PST 24
Peak memory 339236 kb
Host smart-89c0aa22-68fe-45f6-9991-0974fefdd6c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4118185671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_384.4118185671 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_512.3787715222
Short name T785
Test name
Test status
Simulation time 53031585180 ps
CPU time 1421.57 seconds
Started Feb 25 02:03:29 PM PST 24
Finished Feb 25 02:27:11 PM PST 24
Peak memory 297484 kb
Host smart-ee4dbd7a-27a6-4397-9d2e-47dd5ee0026a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3787715222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_512.3787715222 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/43.kmac_test_vectors_shake_128.1317343401
Short name T869
Test name
Test status
Simulation time 264513640545 ps
CPU time 5717.11 seconds
Started Feb 25 02:03:30 PM PST 24
Finished Feb 25 03:38:49 PM PST 24
Peak memory 642516 kb
Host smart-8e83e325-1825-4136-a3e3-c6a5bc24e1b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1317343401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_128.1317343401 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/43.kmac_test_vectors_shake_256.1408793795
Short name T639
Test name
Test status
Simulation time 54275503326 ps
CPU time 4457.93 seconds
Started Feb 25 02:03:27 PM PST 24
Finished Feb 25 03:17:47 PM PST 24
Peak memory 572880 kb
Host smart-8e80c93f-68eb-4b0c-9be7-f5ec81dbb48e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1408793795 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_256.1408793795 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/44.kmac_alert_test.3798062263
Short name T287
Test name
Test status
Simulation time 20277028 ps
CPU time 0.8 seconds
Started Feb 25 02:03:44 PM PST 24
Finished Feb 25 02:03:45 PM PST 24
Peak memory 218076 kb
Host smart-1815ed0e-0f19-49db-beb1-c7569ebd91df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798062263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.3798062263 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_alert_test/latest


Test location /workspace/coverage/default/44.kmac_app.1042426823
Short name T1032
Test name
Test status
Simulation time 4120911450 ps
CPU time 66.95 seconds
Started Feb 25 02:03:43 PM PST 24
Finished Feb 25 02:04:51 PM PST 24
Peak memory 231360 kb
Host smart-8e1e0e4b-f19b-4476-a746-810f2c772337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042426823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.1042426823 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_app/latest


Test location /workspace/coverage/default/44.kmac_burst_write.597827720
Short name T735
Test name
Test status
Simulation time 5092510827 ps
CPU time 609.11 seconds
Started Feb 25 02:03:32 PM PST 24
Finished Feb 25 02:13:41 PM PST 24
Peak memory 234536 kb
Host smart-2c796ef3-38cb-472b-bd8d-3669dd6894ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597827720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.597827720 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_burst_write/latest


Test location /workspace/coverage/default/44.kmac_entropy_refresh.4246164248
Short name T435
Test name
Test status
Simulation time 647176994 ps
CPU time 13.02 seconds
Started Feb 25 02:03:44 PM PST 24
Finished Feb 25 02:03:57 PM PST 24
Peak memory 236720 kb
Host smart-e52f01b5-f606-454f-8dd9-835a17f72164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246164248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.4246164248 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/44.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/44.kmac_error.608561626
Short name T130
Test name
Test status
Simulation time 20678117600 ps
CPU time 284.44 seconds
Started Feb 25 02:03:41 PM PST 24
Finished Feb 25 02:08:26 PM PST 24
Peak memory 259448 kb
Host smart-c65758f4-5d47-4fef-ad37-bad755d458a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608561626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.608561626 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_error/latest


Test location /workspace/coverage/default/44.kmac_key_error.361312489
Short name T697
Test name
Test status
Simulation time 7016369197 ps
CPU time 5.03 seconds
Started Feb 25 02:03:42 PM PST 24
Finished Feb 25 02:03:47 PM PST 24
Peak memory 218380 kb
Host smart-3905da41-ddb1-4461-8450-f8ded5fdf683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361312489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.361312489 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_key_error/latest


Test location /workspace/coverage/default/44.kmac_lc_escalation.1622804125
Short name T847
Test name
Test status
Simulation time 33031304 ps
CPU time 1.43 seconds
Started Feb 25 02:03:41 PM PST 24
Finished Feb 25 02:03:42 PM PST 24
Peak memory 219264 kb
Host smart-14cee5e0-bf5c-4dc4-a468-9c0ee7e6d70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622804125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.1622804125 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/44.kmac_lc_escalation/latest


Test location /workspace/coverage/default/44.kmac_long_msg_and_output.903024818
Short name T218
Test name
Test status
Simulation time 15316367030 ps
CPU time 507.69 seconds
Started Feb 25 02:03:32 PM PST 24
Finished Feb 25 02:12:00 PM PST 24
Peak memory 267124 kb
Host smart-57098b1e-aa76-470d-8b8c-8311a3b415fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903024818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_an
d_output.903024818 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/44.kmac_sideload.4264873379
Short name T736
Test name
Test status
Simulation time 10097353482 ps
CPU time 458.96 seconds
Started Feb 25 02:03:31 PM PST 24
Finished Feb 25 02:11:10 PM PST 24
Peak memory 253376 kb
Host smart-2f8d7565-0279-40ed-a9d3-75be59dd54a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264873379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.4264873379 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_sideload/latest


Test location /workspace/coverage/default/44.kmac_smoke.2972845735
Short name T373
Test name
Test status
Simulation time 1689182812 ps
CPU time 63.92 seconds
Started Feb 25 02:03:34 PM PST 24
Finished Feb 25 02:04:38 PM PST 24
Peak memory 226408 kb
Host smart-ff50be1a-46c5-41b5-a74f-7e76ff7f1302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972845735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.2972845735 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_smoke/latest


Test location /workspace/coverage/default/44.kmac_test_vectors_kmac.121407417
Short name T786
Test name
Test status
Simulation time 817479249 ps
CPU time 6.01 seconds
Started Feb 25 02:03:42 PM PST 24
Finished Feb 25 02:03:48 PM PST 24
Peak memory 218424 kb
Host smart-5d727329-8438-40ed-a993-b2ade0df2bcd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121407417 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.kmac_test_vectors_kmac.121407417 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/44.kmac_test_vectors_kmac_xof.1865838546
Short name T831
Test name
Test status
Simulation time 358985330 ps
CPU time 5.88 seconds
Started Feb 25 02:03:44 PM PST 24
Finished Feb 25 02:03:50 PM PST 24
Peak memory 218364 kb
Host smart-fd155cb9-fed8-434c-a5f8-60f255391bc0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865838546 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.kmac_test_vectors_kmac_xof.1865838546 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_224.1908063175
Short name T980
Test name
Test status
Simulation time 451189015923 ps
CPU time 2341.78 seconds
Started Feb 25 02:03:31 PM PST 24
Finished Feb 25 02:42:34 PM PST 24
Peak memory 403588 kb
Host smart-5663ac85-7125-4f67-8f8c-34a6634d7b94
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1908063175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_224.1908063175 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_256.2496306294
Short name T356
Test name
Test status
Simulation time 63755344314 ps
CPU time 2209.02 seconds
Started Feb 25 02:03:33 PM PST 24
Finished Feb 25 02:40:22 PM PST 24
Peak memory 384664 kb
Host smart-23be60ad-5203-4b12-8cc3-84b5fb189291
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2496306294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_256.2496306294 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_384.146139028
Short name T195
Test name
Test status
Simulation time 50379649390 ps
CPU time 1501.12 seconds
Started Feb 25 02:03:31 PM PST 24
Finished Feb 25 02:28:33 PM PST 24
Peak memory 344132 kb
Host smart-d18bba6b-2067-4724-897f-178917e4f94c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=146139028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_384.146139028 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_512.898135563
Short name T950
Test name
Test status
Simulation time 21378986681 ps
CPU time 1180.77 seconds
Started Feb 25 02:03:31 PM PST 24
Finished Feb 25 02:23:12 PM PST 24
Peak memory 304428 kb
Host smart-b389dd9f-26f1-4e32-a6a2-416fae79c081
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=898135563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_512.898135563 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/44.kmac_test_vectors_shake_128.3396973472
Short name T730
Test name
Test status
Simulation time 540704540555 ps
CPU time 5670.94 seconds
Started Feb 25 02:03:44 PM PST 24
Finished Feb 25 03:38:16 PM PST 24
Peak memory 657596 kb
Host smart-58e529cc-007d-4858-934f-9ea501388d5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3396973472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_128.3396973472 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/44.kmac_test_vectors_shake_256.437980352
Short name T131
Test name
Test status
Simulation time 160974580464 ps
CPU time 4845.26 seconds
Started Feb 25 02:03:43 PM PST 24
Finished Feb 25 03:24:29 PM PST 24
Peak memory 576736 kb
Host smart-3a01cf4f-1cb0-4153-bcb5-d1f6a80267be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=437980352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_256.437980352 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/45.kmac_alert_test.2449184467
Short name T134
Test name
Test status
Simulation time 13785210 ps
CPU time 0.83 seconds
Started Feb 25 02:04:09 PM PST 24
Finished Feb 25 02:04:10 PM PST 24
Peak memory 219272 kb
Host smart-75a3b9ec-e771-4e3f-bc14-003494661ec9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449184467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.2449184467 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_alert_test/latest


Test location /workspace/coverage/default/45.kmac_app.3696865814
Short name T455
Test name
Test status
Simulation time 1920206512 ps
CPU time 62.06 seconds
Started Feb 25 02:03:50 PM PST 24
Finished Feb 25 02:04:52 PM PST 24
Peak memory 228424 kb
Host smart-1d700b71-0b3b-470c-bde5-3e143fadb160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696865814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.3696865814 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_app/latest


Test location /workspace/coverage/default/45.kmac_burst_write.1389747981
Short name T146
Test name
Test status
Simulation time 88743711201 ps
CPU time 1041.12 seconds
Started Feb 25 02:03:45 PM PST 24
Finished Feb 25 02:21:07 PM PST 24
Peak memory 238272 kb
Host smart-c71e9839-a618-47a6-a1a5-112fa3337959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389747981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.1389747981 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_burst_write/latest


Test location /workspace/coverage/default/45.kmac_entropy_refresh.1873120367
Short name T427
Test name
Test status
Simulation time 2437302260 ps
CPU time 66.86 seconds
Started Feb 25 02:03:52 PM PST 24
Finished Feb 25 02:04:59 PM PST 24
Peak memory 230496 kb
Host smart-9c2936a8-9261-4e25-bf07-057176fef7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873120367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.1873120367 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/45.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/45.kmac_error.3254251867
Short name T795
Test name
Test status
Simulation time 14808810880 ps
CPU time 432.16 seconds
Started Feb 25 02:03:49 PM PST 24
Finished Feb 25 02:11:01 PM PST 24
Peak memory 259272 kb
Host smart-3fa07264-c2e7-4d58-bb27-9e8c0f846666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254251867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.3254251867 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_error/latest


Test location /workspace/coverage/default/45.kmac_key_error.2274201163
Short name T583
Test name
Test status
Simulation time 755042768 ps
CPU time 4.77 seconds
Started Feb 25 02:03:53 PM PST 24
Finished Feb 25 02:03:58 PM PST 24
Peak memory 218348 kb
Host smart-33042e54-8610-4c92-ab9a-e35fb65b337d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274201163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.2274201163 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_key_error/latest


Test location /workspace/coverage/default/45.kmac_lc_escalation.354435802
Short name T67
Test name
Test status
Simulation time 36758309 ps
CPU time 1.39 seconds
Started Feb 25 02:04:05 PM PST 24
Finished Feb 25 02:04:08 PM PST 24
Peak memory 219744 kb
Host smart-759e289a-08b1-4741-88e0-4ed77864314b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354435802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.354435802 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/45.kmac_lc_escalation/latest


Test location /workspace/coverage/default/45.kmac_long_msg_and_output.1340658715
Short name T388
Test name
Test status
Simulation time 43878759424 ps
CPU time 1449.82 seconds
Started Feb 25 02:03:42 PM PST 24
Finished Feb 25 02:27:52 PM PST 24
Peak memory 341592 kb
Host smart-bdfb89ad-4597-4c37-a360-74e83acf1181
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340658715 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_a
nd_output.1340658715 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/45.kmac_sideload.4139050745
Short name T476
Test name
Test status
Simulation time 44739157376 ps
CPU time 551.13 seconds
Started Feb 25 02:03:41 PM PST 24
Finished Feb 25 02:12:52 PM PST 24
Peak memory 254840 kb
Host smart-7a9511df-c729-4d55-a22d-8cd079cb077c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139050745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.4139050745 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_sideload/latest


Test location /workspace/coverage/default/45.kmac_smoke.1523121735
Short name T752
Test name
Test status
Simulation time 1820068978 ps
CPU time 68.75 seconds
Started Feb 25 02:03:42 PM PST 24
Finished Feb 25 02:04:51 PM PST 24
Peak memory 226560 kb
Host smart-9a8d32f0-cf1f-4eb5-afed-4436f619ccf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523121735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.1523121735 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_smoke/latest


Test location /workspace/coverage/default/45.kmac_stress_all.2139706611
Short name T113
Test name
Test status
Simulation time 100231899968 ps
CPU time 680.47 seconds
Started Feb 25 02:04:05 PM PST 24
Finished Feb 25 02:15:27 PM PST 24
Peak memory 275940 kb
Host smart-284d2115-8b1c-48a0-a03b-2e2412bd54b8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2139706611 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.2139706611 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_stress_all/latest


Test location /workspace/coverage/default/45.kmac_stress_all_with_rand_reset.3900839174
Short name T127
Test name
Test status
Simulation time 224371289334 ps
CPU time 958.18 seconds
Started Feb 25 02:04:01 PM PST 24
Finished Feb 25 02:20:01 PM PST 24
Peak memory 268492 kb
Host smart-410c0f08-fc11-4e2f-9dbd-f3c837e48fb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3900839174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all_with_rand_reset.3900839174 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/45.kmac_test_vectors_kmac.301467126
Short name T401
Test name
Test status
Simulation time 727689087 ps
CPU time 6.87 seconds
Started Feb 25 02:03:50 PM PST 24
Finished Feb 25 02:03:57 PM PST 24
Peak memory 219836 kb
Host smart-810e8be4-c367-4f6e-bb7b-ab9496faf5bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301467126 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.kmac_test_vectors_kmac.301467126 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/45.kmac_test_vectors_kmac_xof.3139994663
Short name T399
Test name
Test status
Simulation time 130377846 ps
CPU time 5.53 seconds
Started Feb 25 02:03:52 PM PST 24
Finished Feb 25 02:03:57 PM PST 24
Peak memory 219712 kb
Host smart-f351a4fc-5b28-439a-a3ed-e7b19f57e07a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139994663 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.kmac_test_vectors_kmac_xof.3139994663 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_224.3281780365
Short name T346
Test name
Test status
Simulation time 179702787530 ps
CPU time 2273.13 seconds
Started Feb 25 02:03:41 PM PST 24
Finished Feb 25 02:41:34 PM PST 24
Peak memory 398244 kb
Host smart-e81a00b8-e3c3-4e54-ba84-816e1923aad5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3281780365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_224.3281780365 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_256.3727086421
Short name T818
Test name
Test status
Simulation time 728023934821 ps
CPU time 2351.83 seconds
Started Feb 25 02:03:42 PM PST 24
Finished Feb 25 02:42:54 PM PST 24
Peak memory 390248 kb
Host smart-d6202a49-b653-4c4c-a17a-e5cc1f06050b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3727086421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_256.3727086421 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_384.122765835
Short name T892
Test name
Test status
Simulation time 286107768852 ps
CPU time 1831.4 seconds
Started Feb 25 02:03:45 PM PST 24
Finished Feb 25 02:34:17 PM PST 24
Peak memory 334316 kb
Host smart-f1cbd1f3-2002-4440-8fa2-fc3f8508ea3c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=122765835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_384.122765835 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_512.1085416306
Short name T556
Test name
Test status
Simulation time 196858299813 ps
CPU time 1452.18 seconds
Started Feb 25 02:03:52 PM PST 24
Finished Feb 25 02:28:04 PM PST 24
Peak memory 302372 kb
Host smart-d78c077f-c264-4595-b7fa-73e69cf997f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1085416306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_512.1085416306 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/45.kmac_test_vectors_shake_128.2761008967
Short name T111
Test name
Test status
Simulation time 375078139461 ps
CPU time 6070.17 seconds
Started Feb 25 02:03:52 PM PST 24
Finished Feb 25 03:45:03 PM PST 24
Peak memory 649764 kb
Host smart-8868fd0b-3f08-4910-9682-ab98a0cb6a25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2761008967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_128.2761008967 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/45.kmac_test_vectors_shake_256.710511683
Short name T219
Test name
Test status
Simulation time 153062938783 ps
CPU time 5250.82 seconds
Started Feb 25 02:03:52 PM PST 24
Finished Feb 25 03:31:24 PM PST 24
Peak memory 563700 kb
Host smart-5aaab730-0004-4a3e-ac75-adeb08f67b33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=710511683 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_256.710511683 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/46.kmac_alert_test.646280826
Short name T826
Test name
Test status
Simulation time 31582879 ps
CPU time 0.8 seconds
Started Feb 25 02:04:28 PM PST 24
Finished Feb 25 02:04:29 PM PST 24
Peak memory 218076 kb
Host smart-df013852-5a7a-4113-b678-585ef1e8ae82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646280826 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.646280826 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/46.kmac_alert_test/latest


Test location /workspace/coverage/default/46.kmac_app.544862947
Short name T256
Test name
Test status
Simulation time 7575136294 ps
CPU time 195.05 seconds
Started Feb 25 02:04:27 PM PST 24
Finished Feb 25 02:07:43 PM PST 24
Peak memory 240548 kb
Host smart-e7c1d0f5-7ce1-440d-9401-e4f6585af638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544862947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.544862947 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_app/latest


Test location /workspace/coverage/default/46.kmac_burst_write.3513574800
Short name T1026
Test name
Test status
Simulation time 31473848172 ps
CPU time 765.61 seconds
Started Feb 25 02:04:12 PM PST 24
Finished Feb 25 02:16:57 PM PST 24
Peak memory 237628 kb
Host smart-38ae7dc6-9a80-4a61-9a6e-540121f7eb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513574800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.3513574800 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_burst_write/latest


Test location /workspace/coverage/default/46.kmac_entropy_refresh.4016577149
Short name T313
Test name
Test status
Simulation time 12461723256 ps
CPU time 92.62 seconds
Started Feb 25 02:04:28 PM PST 24
Finished Feb 25 02:06:01 PM PST 24
Peak memory 243080 kb
Host smart-da9f30d8-c701-48b1-a0fd-6b59bda797ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016577149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.4016577149 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/46.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/46.kmac_error.3564564869
Short name T557
Test name
Test status
Simulation time 48309080498 ps
CPU time 448.77 seconds
Started Feb 25 02:04:20 PM PST 24
Finished Feb 25 02:11:49 PM PST 24
Peak memory 275032 kb
Host smart-56054c1b-11d6-4c24-9e77-5173885ffd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564564869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.3564564869 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_error/latest


Test location /workspace/coverage/default/46.kmac_key_error.1034052814
Short name T614
Test name
Test status
Simulation time 2834780955 ps
CPU time 5.35 seconds
Started Feb 25 02:04:30 PM PST 24
Finished Feb 25 02:04:36 PM PST 24
Peak memory 218376 kb
Host smart-0f5b9541-e4c7-4499-9d8e-73bc69e5cc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034052814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.1034052814 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_key_error/latest


Test location /workspace/coverage/default/46.kmac_lc_escalation.2978673822
Short name T17
Test name
Test status
Simulation time 49533378 ps
CPU time 1.37 seconds
Started Feb 25 02:04:29 PM PST 24
Finished Feb 25 02:04:30 PM PST 24
Peak memory 219316 kb
Host smart-1b58c549-5b8b-47bd-9faa-b1e3572d32ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978673822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.2978673822 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/46.kmac_lc_escalation/latest


Test location /workspace/coverage/default/46.kmac_long_msg_and_output.106968983
Short name T158
Test name
Test status
Simulation time 89300250570 ps
CPU time 2717.08 seconds
Started Feb 25 02:04:05 PM PST 24
Finished Feb 25 02:49:24 PM PST 24
Peak memory 427404 kb
Host smart-959dff06-4a45-4adb-a60a-aa908bf35b0d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106968983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_an
d_output.106968983 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/46.kmac_sideload.2649145480
Short name T836
Test name
Test status
Simulation time 3636508216 ps
CPU time 330.86 seconds
Started Feb 25 02:04:02 PM PST 24
Finished Feb 25 02:09:33 PM PST 24
Peak memory 246128 kb
Host smart-8e98d823-e67e-456d-a5d9-d9e9a3bc7f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649145480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.2649145480 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_sideload/latest


Test location /workspace/coverage/default/46.kmac_smoke.1173344816
Short name T393
Test name
Test status
Simulation time 80727650 ps
CPU time 4.21 seconds
Started Feb 25 02:04:09 PM PST 24
Finished Feb 25 02:04:13 PM PST 24
Peak memory 224280 kb
Host smart-fe4f41c8-0a7b-4e91-b0c3-6bf714ce928e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173344816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.1173344816 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_smoke/latest


Test location /workspace/coverage/default/46.kmac_stress_all.3727672510
Short name T402
Test name
Test status
Simulation time 30498222775 ps
CPU time 477.68 seconds
Started Feb 25 02:04:27 PM PST 24
Finished Feb 25 02:12:26 PM PST 24
Peak memory 275716 kb
Host smart-3b9b30e3-7975-4f29-ad8c-557bef0a0641
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3727672510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.3727672510 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_stress_all/latest


Test location /workspace/coverage/default/46.kmac_test_vectors_kmac.322427961
Short name T431
Test name
Test status
Simulation time 409570521 ps
CPU time 6.97 seconds
Started Feb 25 02:04:19 PM PST 24
Finished Feb 25 02:04:28 PM PST 24
Peak memory 219644 kb
Host smart-2373c672-41cc-409c-a23f-21f0c3dc8e98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322427961 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.kmac_test_vectors_kmac.322427961 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/46.kmac_test_vectors_kmac_xof.2913290948
Short name T161
Test name
Test status
Simulation time 256100098 ps
CPU time 6.18 seconds
Started Feb 25 02:04:28 PM PST 24
Finished Feb 25 02:04:34 PM PST 24
Peak memory 218080 kb
Host smart-a8c2aa56-65e7-4793-9325-a55554f4ecf2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913290948 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.kmac_test_vectors_kmac_xof.2913290948 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_224.2561640639
Short name T112
Test name
Test status
Simulation time 80631847467 ps
CPU time 2091.56 seconds
Started Feb 25 02:04:12 PM PST 24
Finished Feb 25 02:39:04 PM PST 24
Peak memory 396848 kb
Host smart-892f9fac-c78e-4aab-ba4d-f6cc8451a882
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2561640639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_224.2561640639 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_256.3559782876
Short name T275
Test name
Test status
Simulation time 1523177771543 ps
CPU time 2977.24 seconds
Started Feb 25 02:04:14 PM PST 24
Finished Feb 25 02:53:51 PM PST 24
Peak memory 386792 kb
Host smart-e77fec3a-58cc-4086-beae-805da2f5174e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3559782876 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_256.3559782876 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_384.281769490
Short name T753
Test name
Test status
Simulation time 15689368271 ps
CPU time 1703.43 seconds
Started Feb 25 02:04:12 PM PST 24
Finished Feb 25 02:32:37 PM PST 24
Peak memory 347804 kb
Host smart-9fc96661-787a-497b-a6e5-58b2416bd09a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=281769490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_384.281769490 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_512.412758598
Short name T852
Test name
Test status
Simulation time 44439369572 ps
CPU time 1069.17 seconds
Started Feb 25 02:04:26 PM PST 24
Finished Feb 25 02:22:15 PM PST 24
Peak memory 294448 kb
Host smart-66f82a61-8afe-41ab-a0a4-8f82f269e0b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=412758598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_512.412758598 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/46.kmac_test_vectors_shake_128.3000651931
Short name T627
Test name
Test status
Simulation time 240471664421 ps
CPU time 6161.72 seconds
Started Feb 25 02:04:27 PM PST 24
Finished Feb 25 03:47:10 PM PST 24
Peak memory 653380 kb
Host smart-09d2f427-318e-470d-ae7d-eb015369a733
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3000651931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_128.3000651931 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/46.kmac_test_vectors_shake_256.1517352298
Short name T622
Test name
Test status
Simulation time 586452477712 ps
CPU time 4319.02 seconds
Started Feb 25 02:04:20 PM PST 24
Finished Feb 25 03:16:20 PM PST 24
Peak memory 580132 kb
Host smart-1fc135ec-1880-44f4-bc8a-58ef9f4319e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1517352298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_256.1517352298 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/47.kmac_alert_test.2370755412
Short name T100
Test name
Test status
Simulation time 17851547 ps
CPU time 0.9 seconds
Started Feb 25 02:04:50 PM PST 24
Finished Feb 25 02:04:52 PM PST 24
Peak memory 218212 kb
Host smart-0ffc8c7a-818c-42cb-86d2-b577f5922437
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370755412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.2370755412 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_alert_test/latest


Test location /workspace/coverage/default/47.kmac_app.3083745779
Short name T675
Test name
Test status
Simulation time 2995459342 ps
CPU time 129.34 seconds
Started Feb 25 02:04:42 PM PST 24
Finished Feb 25 02:06:53 PM PST 24
Peak memory 236884 kb
Host smart-ba819307-3ca0-404f-93fe-25826b988240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083745779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.3083745779 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_app/latest


Test location /workspace/coverage/default/47.kmac_burst_write.1436310103
Short name T387
Test name
Test status
Simulation time 711263269 ps
CPU time 22.26 seconds
Started Feb 25 02:04:29 PM PST 24
Finished Feb 25 02:04:52 PM PST 24
Peak memory 226972 kb
Host smart-c74c9ba1-5f59-484c-a27b-20347722b56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436310103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.1436310103 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_burst_write/latest


Test location /workspace/coverage/default/47.kmac_entropy_refresh.4226143235
Short name T79
Test name
Test status
Simulation time 8918403381 ps
CPU time 246.63 seconds
Started Feb 25 02:04:39 PM PST 24
Finished Feb 25 02:08:46 PM PST 24
Peak memory 246564 kb
Host smart-62a450a4-20eb-411c-b421-0e0d18ba9716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226143235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.4226143235 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/47.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/47.kmac_error.1381676242
Short name T655
Test name
Test status
Simulation time 89681956651 ps
CPU time 593.38 seconds
Started Feb 25 02:04:45 PM PST 24
Finished Feb 25 02:14:38 PM PST 24
Peak memory 269200 kb
Host smart-760bfe42-dd8d-475c-aa72-f141a330263c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381676242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.1381676242 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_error/latest


Test location /workspace/coverage/default/47.kmac_key_error.369365779
Short name T42
Test name
Test status
Simulation time 1062962444 ps
CPU time 6.67 seconds
Started Feb 25 02:04:39 PM PST 24
Finished Feb 25 02:04:45 PM PST 24
Peak memory 218316 kb
Host smart-37033f88-96b1-4f89-ac2f-a0c6da8de804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369365779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.369365779 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_key_error/latest


Test location /workspace/coverage/default/47.kmac_lc_escalation.3700540887
Short name T857
Test name
Test status
Simulation time 72784855 ps
CPU time 1.51 seconds
Started Feb 25 02:04:40 PM PST 24
Finished Feb 25 02:04:42 PM PST 24
Peak memory 219568 kb
Host smart-606f4704-7001-4ee4-b5e0-a3d61cc61e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700540887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.3700540887 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/47.kmac_lc_escalation/latest


Test location /workspace/coverage/default/47.kmac_long_msg_and_output.3183468108
Short name T865
Test name
Test status
Simulation time 820549770961 ps
CPU time 3134.23 seconds
Started Feb 25 02:04:30 PM PST 24
Finished Feb 25 02:56:45 PM PST 24
Peak memory 460968 kb
Host smart-95e2b9c0-7197-4db9-ac48-1d0b9516cb43
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183468108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_a
nd_output.3183468108 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/47.kmac_sideload.1541295615
Short name T589
Test name
Test status
Simulation time 2843384626 ps
CPU time 136.18 seconds
Started Feb 25 02:04:28 PM PST 24
Finished Feb 25 02:06:45 PM PST 24
Peak memory 234156 kb
Host smart-03583a57-e563-4dfb-bcd1-8b95f3c52966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541295615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.1541295615 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_sideload/latest


Test location /workspace/coverage/default/47.kmac_smoke.467991499
Short name T811
Test name
Test status
Simulation time 3388112904 ps
CPU time 75.96 seconds
Started Feb 25 02:04:27 PM PST 24
Finished Feb 25 02:05:44 PM PST 24
Peak memory 220504 kb
Host smart-16a7c875-5c24-4ad4-bb62-7219435f2b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467991499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.467991499 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_smoke/latest


Test location /workspace/coverage/default/47.kmac_stress_all.1056451333
Short name T872
Test name
Test status
Simulation time 113305398038 ps
CPU time 2162.46 seconds
Started Feb 25 02:04:55 PM PST 24
Finished Feb 25 02:40:58 PM PST 24
Peak memory 434556 kb
Host smart-9737df8f-9110-4014-ac5a-9b868d3ca5bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1056451333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.1056451333 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_stress_all/latest


Test location /workspace/coverage/default/47.kmac_test_vectors_kmac.1862871976
Short name T767
Test name
Test status
Simulation time 209387107 ps
CPU time 5.8 seconds
Started Feb 25 02:04:38 PM PST 24
Finished Feb 25 02:04:44 PM PST 24
Peak memory 219784 kb
Host smart-465da7b6-63b2-49a4-a146-813290d3be55
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862871976 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.kmac_test_vectors_kmac.1862871976 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/47.kmac_test_vectors_kmac_xof.3542247602
Short name T803
Test name
Test status
Simulation time 113690896 ps
CPU time 5.85 seconds
Started Feb 25 02:04:39 PM PST 24
Finished Feb 25 02:04:45 PM PST 24
Peak memory 219916 kb
Host smart-a9d3df23-1d92-4e3a-bf81-1b1a3e879302
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542247602 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.kmac_test_vectors_kmac_xof.3542247602 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_224.402505148
Short name T784
Test name
Test status
Simulation time 48199123724 ps
CPU time 1930.61 seconds
Started Feb 25 02:04:30 PM PST 24
Finished Feb 25 02:36:41 PM PST 24
Peak memory 393816 kb
Host smart-8efa6949-ab12-4f2a-b59f-eb2bee25ed1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=402505148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_224.402505148 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_256.932462501
Short name T307
Test name
Test status
Simulation time 247568199442 ps
CPU time 2317.4 seconds
Started Feb 25 02:04:30 PM PST 24
Finished Feb 25 02:43:08 PM PST 24
Peak memory 387812 kb
Host smart-bd352bfe-ec85-43d9-82de-d642feb47ad6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=932462501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_256.932462501 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_384.2911471682
Short name T539
Test name
Test status
Simulation time 205456863090 ps
CPU time 1776.97 seconds
Started Feb 25 02:04:39 PM PST 24
Finished Feb 25 02:34:16 PM PST 24
Peak memory 333908 kb
Host smart-77c7e964-d2b4-4d6f-8f47-624ffb229273
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2911471682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_384.2911471682 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_512.1173630472
Short name T310
Test name
Test status
Simulation time 44062672444 ps
CPU time 1205.53 seconds
Started Feb 25 02:04:39 PM PST 24
Finished Feb 25 02:24:45 PM PST 24
Peak memory 302744 kb
Host smart-5716e2be-cbf6-49c4-a4f1-04c16e420f93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1173630472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_512.1173630472 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/47.kmac_test_vectors_shake_128.2785218736
Short name T87
Test name
Test status
Simulation time 183046394131 ps
CPU time 6123.55 seconds
Started Feb 25 02:04:41 PM PST 24
Finished Feb 25 03:46:45 PM PST 24
Peak memory 653676 kb
Host smart-2b168af2-594e-417b-84b0-1fdd4730f73c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2785218736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_128.2785218736 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/47.kmac_test_vectors_shake_256.1818314271
Short name T1039
Test name
Test status
Simulation time 613662534653 ps
CPU time 5124.85 seconds
Started Feb 25 02:04:39 PM PST 24
Finished Feb 25 03:30:05 PM PST 24
Peak memory 567084 kb
Host smart-2243fe8e-4e50-4ffc-8d72-727e7dfed178
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1818314271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_256.1818314271 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/48.kmac_alert_test.1468440384
Short name T540
Test name
Test status
Simulation time 56687934 ps
CPU time 0.89 seconds
Started Feb 25 02:05:13 PM PST 24
Finished Feb 25 02:05:15 PM PST 24
Peak memory 219312 kb
Host smart-0a6ed561-7415-492c-bb05-835caf5f57df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468440384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.1468440384 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_alert_test/latest


Test location /workspace/coverage/default/48.kmac_app.2193645830
Short name T977
Test name
Test status
Simulation time 6033395450 ps
CPU time 187.84 seconds
Started Feb 25 02:05:08 PM PST 24
Finished Feb 25 02:08:17 PM PST 24
Peak memory 240164 kb
Host smart-7c291565-68d0-4cbc-98ec-381061bbc8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193645830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.2193645830 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_app/latest


Test location /workspace/coverage/default/48.kmac_burst_write.2207548732
Short name T930
Test name
Test status
Simulation time 9980631720 ps
CPU time 1009.07 seconds
Started Feb 25 02:05:04 PM PST 24
Finished Feb 25 02:21:53 PM PST 24
Peak memory 237248 kb
Host smart-f0726a7f-b93e-4f7f-9541-b2858f699595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207548732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.2207548732 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_burst_write/latest


Test location /workspace/coverage/default/48.kmac_entropy_refresh.3954055491
Short name T80
Test name
Test status
Simulation time 6257358735 ps
CPU time 161.86 seconds
Started Feb 25 02:05:10 PM PST 24
Finished Feb 25 02:07:52 PM PST 24
Peak memory 243008 kb
Host smart-9918105f-5ed0-455a-9296-730f6217eb2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954055491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.3954055491 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/48.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/48.kmac_error.812990778
Short name T638
Test name
Test status
Simulation time 5589143329 ps
CPU time 508.32 seconds
Started Feb 25 02:05:13 PM PST 24
Finished Feb 25 02:13:42 PM PST 24
Peak memory 269484 kb
Host smart-a834d1c5-c248-43e8-814a-7f641bb2ab71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812990778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.812990778 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_error/latest


Test location /workspace/coverage/default/48.kmac_key_error.63349719
Short name T965
Test name
Test status
Simulation time 81367233 ps
CPU time 1.13 seconds
Started Feb 25 02:05:13 PM PST 24
Finished Feb 25 02:05:14 PM PST 24
Peak memory 218228 kb
Host smart-cc72fe25-f633-41ec-ae61-1919341211c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63349719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.63349719 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_key_error/latest


Test location /workspace/coverage/default/48.kmac_lc_escalation.3939209456
Short name T15
Test name
Test status
Simulation time 7266619898 ps
CPU time 23.46 seconds
Started Feb 25 02:05:10 PM PST 24
Finished Feb 25 02:05:34 PM PST 24
Peak memory 234880 kb
Host smart-7b48575a-b78a-4c22-8b24-4cc198179187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939209456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.3939209456 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/48.kmac_lc_escalation/latest


Test location /workspace/coverage/default/48.kmac_long_msg_and_output.1788670885
Short name T783
Test name
Test status
Simulation time 128893847859 ps
CPU time 3555.89 seconds
Started Feb 25 02:04:55 PM PST 24
Finished Feb 25 03:04:12 PM PST 24
Peak memory 474188 kb
Host smart-5a5ad54d-9467-422f-8f6e-0c92372daaa9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788670885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_a
nd_output.1788670885 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/48.kmac_sideload.2931933213
Short name T698
Test name
Test status
Simulation time 30827568662 ps
CPU time 331.18 seconds
Started Feb 25 02:04:51 PM PST 24
Finished Feb 25 02:10:23 PM PST 24
Peak memory 249048 kb
Host smart-d85ee50a-7b77-4eaf-89c7-1fb544133b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931933213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.2931933213 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_sideload/latest


Test location /workspace/coverage/default/48.kmac_smoke.2681687346
Short name T546
Test name
Test status
Simulation time 5724317859 ps
CPU time 34.11 seconds
Started Feb 25 02:04:52 PM PST 24
Finished Feb 25 02:05:26 PM PST 24
Peak memory 226588 kb
Host smart-7456c393-df6b-4169-b4ed-75727ddad1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681687346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.2681687346 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_smoke/latest


Test location /workspace/coverage/default/48.kmac_stress_all.4104287773
Short name T1010
Test name
Test status
Simulation time 42360349569 ps
CPU time 1495.24 seconds
Started Feb 25 02:05:16 PM PST 24
Finished Feb 25 02:30:12 PM PST 24
Peak memory 373276 kb
Host smart-2645756f-eaf8-4628-baf5-439e00bd7f3d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4104287773 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.4104287773 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_stress_all/latest


Test location /workspace/coverage/default/48.kmac_test_vectors_kmac.3819081524
Short name T702
Test name
Test status
Simulation time 475571495 ps
CPU time 5.9 seconds
Started Feb 25 02:05:08 PM PST 24
Finished Feb 25 02:05:15 PM PST 24
Peak memory 218480 kb
Host smart-6b368953-0898-4e71-902a-05961dca720a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819081524 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.kmac_test_vectors_kmac.3819081524 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/48.kmac_test_vectors_kmac_xof.3491492287
Short name T156
Test name
Test status
Simulation time 212434100 ps
CPU time 6.44 seconds
Started Feb 25 02:05:09 PM PST 24
Finished Feb 25 02:05:16 PM PST 24
Peak memory 218452 kb
Host smart-a1863829-c8e4-4dab-bb19-e07f51649d86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491492287 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.kmac_test_vectors_kmac_xof.3491492287 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_224.3755957982
Short name T217
Test name
Test status
Simulation time 84321078817 ps
CPU time 2072.99 seconds
Started Feb 25 02:04:51 PM PST 24
Finished Feb 25 02:39:24 PM PST 24
Peak memory 399968 kb
Host smart-1e3b8ec1-a33a-41b3-95fc-dfe1343793bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3755957982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_224.3755957982 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_256.1781438355
Short name T899
Test name
Test status
Simulation time 39436658883 ps
CPU time 1937.12 seconds
Started Feb 25 02:04:52 PM PST 24
Finished Feb 25 02:37:09 PM PST 24
Peak memory 382520 kb
Host smart-0d52bf30-6b55-44db-b120-c42903a48092
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1781438355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_256.1781438355 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_384.1300348913
Short name T720
Test name
Test status
Simulation time 280315910343 ps
CPU time 1855.26 seconds
Started Feb 25 02:04:53 PM PST 24
Finished Feb 25 02:35:49 PM PST 24
Peak memory 342956 kb
Host smart-7659eaed-8da3-4bd5-afb5-7079e1464dad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1300348913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_384.1300348913 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_512.3006348770
Short name T305
Test name
Test status
Simulation time 41679626836 ps
CPU time 1057.51 seconds
Started Feb 25 02:04:53 PM PST 24
Finished Feb 25 02:22:31 PM PST 24
Peak memory 300312 kb
Host smart-5908f375-03a5-4503-81c4-44486db993b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3006348770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_512.3006348770 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/48.kmac_test_vectors_shake_128.3753645472
Short name T909
Test name
Test status
Simulation time 870241219958 ps
CPU time 5336.18 seconds
Started Feb 25 02:04:55 PM PST 24
Finished Feb 25 03:33:53 PM PST 24
Peak memory 663968 kb
Host smart-60cd97dc-bdce-4805-bd0e-b145ff63041c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3753645472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_128.3753645472 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/48.kmac_test_vectors_shake_256.60232179
Short name T1035
Test name
Test status
Simulation time 56459904691 ps
CPU time 4786.41 seconds
Started Feb 25 02:05:12 PM PST 24
Finished Feb 25 03:24:59 PM PST 24
Peak memory 579300 kb
Host smart-f53bde97-b8eb-4f0c-b3b2-dc7018a5bb82
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=60232179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_256.60232179 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/49.kmac_alert_test.1962097027
Short name T315
Test name
Test status
Simulation time 22077128 ps
CPU time 0.8 seconds
Started Feb 25 02:05:28 PM PST 24
Finished Feb 25 02:05:29 PM PST 24
Peak memory 219268 kb
Host smart-6373363d-d426-4983-9e8d-d0f7e77f548f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962097027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.1962097027 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_alert_test/latest


Test location /workspace/coverage/default/49.kmac_app.749038861
Short name T428
Test name
Test status
Simulation time 25813118324 ps
CPU time 181.96 seconds
Started Feb 25 02:05:21 PM PST 24
Finished Feb 25 02:08:23 PM PST 24
Peak memory 243096 kb
Host smart-e8e12bb7-7a69-4369-bda5-15b4e8318038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749038861 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.749038861 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_app/latest


Test location /workspace/coverage/default/49.kmac_burst_write.3990203947
Short name T70
Test name
Test status
Simulation time 9452742888 ps
CPU time 322.17 seconds
Started Feb 25 02:05:22 PM PST 24
Finished Feb 25 02:10:45 PM PST 24
Peak memory 238984 kb
Host smart-a9270a48-b21a-416b-9c75-94f23c1c7967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990203947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.3990203947 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_burst_write/latest


Test location /workspace/coverage/default/49.kmac_entropy_refresh.3525553775
Short name T521
Test name
Test status
Simulation time 40974737391 ps
CPU time 288.13 seconds
Started Feb 25 02:05:19 PM PST 24
Finished Feb 25 02:10:09 PM PST 24
Peak memory 245428 kb
Host smart-731cc257-5989-4e0f-a55e-a80f37cb6af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525553775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.3525553775 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/49.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/49.kmac_error.403331434
Short name T169
Test name
Test status
Simulation time 35308554176 ps
CPU time 229.8 seconds
Started Feb 25 02:05:33 PM PST 24
Finished Feb 25 02:09:23 PM PST 24
Peak memory 259248 kb
Host smart-2f75f3d2-e058-4baf-a1bc-10ed0b7e9e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403331434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.403331434 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_error/latest


Test location /workspace/coverage/default/49.kmac_key_error.2536851903
Short name T738
Test name
Test status
Simulation time 646092004 ps
CPU time 2.44 seconds
Started Feb 25 02:05:34 PM PST 24
Finished Feb 25 02:05:37 PM PST 24
Peak memory 218368 kb
Host smart-78b54531-bf02-46ef-b98d-56f60ead457a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536851903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.2536851903 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_key_error/latest


Test location /workspace/coverage/default/49.kmac_lc_escalation.1395006398
Short name T63
Test name
Test status
Simulation time 52298142 ps
CPU time 1.23 seconds
Started Feb 25 02:05:28 PM PST 24
Finished Feb 25 02:05:30 PM PST 24
Peak memory 218364 kb
Host smart-4828783d-905f-4b59-9071-c7f666c76151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395006398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.1395006398 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/49.kmac_lc_escalation/latest


Test location /workspace/coverage/default/49.kmac_long_msg_and_output.2334258071
Short name T631
Test name
Test status
Simulation time 29983885261 ps
CPU time 3001.45 seconds
Started Feb 25 02:05:13 PM PST 24
Finished Feb 25 02:55:15 PM PST 24
Peak memory 465708 kb
Host smart-5ac838fe-dfd7-462a-8b07-d972a2008569
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334258071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_a
nd_output.2334258071 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/49.kmac_sideload.58285838
Short name T661
Test name
Test status
Simulation time 2972711778 ps
CPU time 65.91 seconds
Started Feb 25 02:05:20 PM PST 24
Finished Feb 25 02:06:27 PM PST 24
Peak memory 230244 kb
Host smart-96741b81-7127-4474-a660-628559e508cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58285838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.58285838 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_sideload/latest


Test location /workspace/coverage/default/49.kmac_smoke.2850561617
Short name T545
Test name
Test status
Simulation time 3480003381 ps
CPU time 29.06 seconds
Started Feb 25 02:05:12 PM PST 24
Finished Feb 25 02:05:41 PM PST 24
Peak memory 223756 kb
Host smart-63af0dc6-f8d7-4ea8-8df4-a27699353c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850561617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.2850561617 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_smoke/latest


Test location /workspace/coverage/default/49.kmac_stress_all.634657103
Short name T517
Test name
Test status
Simulation time 117178622837 ps
CPU time 1472.23 seconds
Started Feb 25 02:05:29 PM PST 24
Finished Feb 25 02:30:01 PM PST 24
Peak memory 339800 kb
Host smart-bec49172-8166-4e1d-b728-d21a0d913a3c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=634657103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.634657103 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_stress_all/latest


Test location /workspace/coverage/default/49.kmac_stress_all_with_rand_reset.3675415524
Short name T56
Test name
Test status
Simulation time 146596389288 ps
CPU time 1883.78 seconds
Started Feb 25 02:05:29 PM PST 24
Finished Feb 25 02:36:53 PM PST 24
Peak memory 351976 kb
Host smart-14439997-4d01-4a0b-acbb-578aa635d0d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3675415524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all_with_rand_reset.3675415524 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/49.kmac_test_vectors_kmac.918401222
Short name T340
Test name
Test status
Simulation time 1677185538 ps
CPU time 7.72 seconds
Started Feb 25 02:05:21 PM PST 24
Finished Feb 25 02:05:29 PM PST 24
Peak memory 218476 kb
Host smart-8083a49f-4eb3-44f2-8b80-dc880ccc1309
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918401222 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.kmac_test_vectors_kmac.918401222 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/49.kmac_test_vectors_kmac_xof.2991188535
Short name T205
Test name
Test status
Simulation time 189020084 ps
CPU time 6.13 seconds
Started Feb 25 02:05:19 PM PST 24
Finished Feb 25 02:05:27 PM PST 24
Peak memory 218480 kb
Host smart-e97f7009-30a2-4e37-a1b4-c840b767e8f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991188535 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.kmac_test_vectors_kmac_xof.2991188535 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_224.2046488085
Short name T433
Test name
Test status
Simulation time 462480441043 ps
CPU time 2457.92 seconds
Started Feb 25 02:05:20 PM PST 24
Finished Feb 25 02:46:19 PM PST 24
Peak memory 393028 kb
Host smart-f71e9290-5ade-4b52-ac38-b8cd711df89d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2046488085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_224.2046488085 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_256.501362521
Short name T318
Test name
Test status
Simulation time 412627043683 ps
CPU time 2281.12 seconds
Started Feb 25 02:05:19 PM PST 24
Finished Feb 25 02:43:22 PM PST 24
Peak memory 382204 kb
Host smart-d7bc878a-471f-4849-af13-d76ce777478f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=501362521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_256.501362521 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_384.799099093
Short name T272
Test name
Test status
Simulation time 64645483205 ps
CPU time 1541.07 seconds
Started Feb 25 02:05:21 PM PST 24
Finished Feb 25 02:31:04 PM PST 24
Peak memory 338304 kb
Host smart-0bb157de-baad-488c-b50a-1a7ef0051ad8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=799099093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_384.799099093 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_512.2944957522
Short name T953
Test name
Test status
Simulation time 27230957901 ps
CPU time 1265.4 seconds
Started Feb 25 02:05:21 PM PST 24
Finished Feb 25 02:26:27 PM PST 24
Peak memory 297768 kb
Host smart-eeaad7ce-11fe-4927-8cfd-d662d13c5c85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2944957522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_512.2944957522 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/49.kmac_test_vectors_shake_128.276428776
Short name T202
Test name
Test status
Simulation time 179908176947 ps
CPU time 6083.63 seconds
Started Feb 25 02:05:21 PM PST 24
Finished Feb 25 03:46:46 PM PST 24
Peak memory 651760 kb
Host smart-0b39e5db-512f-4935-a160-e52df2350d9c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=276428776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_128.276428776 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/49.kmac_test_vectors_shake_256.4215208184
Short name T686
Test name
Test status
Simulation time 221384876238 ps
CPU time 4562.61 seconds
Started Feb 25 02:05:21 PM PST 24
Finished Feb 25 03:21:24 PM PST 24
Peak memory 577880 kb
Host smart-17e2b95c-f686-4001-989b-785fcad38692
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4215208184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_256.4215208184 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/5.kmac_alert_test.3310622709
Short name T821
Test name
Test status
Simulation time 24693391 ps
CPU time 0.94 seconds
Started Feb 25 01:55:58 PM PST 24
Finished Feb 25 01:55:59 PM PST 24
Peak memory 218132 kb
Host smart-cba8eccb-0a87-498d-bcb4-8e0cdf8e41c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310622709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.3310622709 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_alert_test/latest


Test location /workspace/coverage/default/5.kmac_app.3775106829
Short name T975
Test name
Test status
Simulation time 9800912323 ps
CPU time 81.08 seconds
Started Feb 25 01:55:40 PM PST 24
Finished Feb 25 01:57:02 PM PST 24
Peak memory 232660 kb
Host smart-dc1fa577-85af-474a-ac04-cd652e7b386e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775106829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.3775106829 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_app/latest


Test location /workspace/coverage/default/5.kmac_burst_write.1664682974
Short name T1009
Test name
Test status
Simulation time 2893700351 ps
CPU time 115.52 seconds
Started Feb 25 01:55:52 PM PST 24
Finished Feb 25 01:57:48 PM PST 24
Peak memory 226984 kb
Host smart-c3c7eb0e-3e05-4955-a3d2-e79f33d1eb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664682974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.1664682974 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_burst_write/latest


Test location /workspace/coverage/default/5.kmac_edn_timeout_error.547711933
Short name T469
Test name
Test status
Simulation time 82873462 ps
CPU time 1.01 seconds
Started Feb 25 01:55:51 PM PST 24
Finished Feb 25 01:55:52 PM PST 24
Peak memory 217964 kb
Host smart-8e225f45-f9a9-401d-a645-730ba5868471
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=547711933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.547711933 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/5.kmac_entropy_mode_error.3578418981
Short name T672
Test name
Test status
Simulation time 97096721 ps
CPU time 1.39 seconds
Started Feb 25 01:55:51 PM PST 24
Finished Feb 25 01:55:53 PM PST 24
Peak memory 217756 kb
Host smart-3fe63070-6309-46d1-b95d-39e2b0fc2bb9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3578418981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.3578418981 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/5.kmac_entropy_ready_error.2359791631
Short name T971
Test name
Test status
Simulation time 28603218364 ps
CPU time 73.23 seconds
Started Feb 25 01:55:53 PM PST 24
Finished Feb 25 01:57:06 PM PST 24
Peak memory 220436 kb
Host smart-11c3190f-4bd6-41a1-be74-76e0f2521dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359791631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.2359791631 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_ready_error/latest


Test location /workspace/coverage/default/5.kmac_entropy_refresh.2777233692
Short name T1005
Test name
Test status
Simulation time 6133399062 ps
CPU time 323.03 seconds
Started Feb 25 01:55:51 PM PST 24
Finished Feb 25 02:01:15 PM PST 24
Peak memory 247336 kb
Host smart-6278c762-8051-42c0-a594-9c73ca8968e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777233692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.2777233692 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/5.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/5.kmac_error.2384009244
Short name T1044
Test name
Test status
Simulation time 13413091507 ps
CPU time 419.89 seconds
Started Feb 25 01:55:58 PM PST 24
Finished Feb 25 02:02:58 PM PST 24
Peak memory 268484 kb
Host smart-49d80387-98a7-4c2d-9879-d36707bab014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384009244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.2384009244 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_error/latest


Test location /workspace/coverage/default/5.kmac_key_error.107360232
Short name T708
Test name
Test status
Simulation time 700924835 ps
CPU time 4.55 seconds
Started Feb 25 01:55:53 PM PST 24
Finished Feb 25 01:55:58 PM PST 24
Peak memory 218220 kb
Host smart-af91511c-a304-4335-a5fa-76d327aefcd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107360232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.107360232 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_key_error/latest


Test location /workspace/coverage/default/5.kmac_lc_escalation.661164119
Short name T403
Test name
Test status
Simulation time 1602330092 ps
CPU time 7.38 seconds
Started Feb 25 01:55:51 PM PST 24
Finished Feb 25 01:55:59 PM PST 24
Peak memory 234172 kb
Host smart-60539dd4-a60b-40b3-aeba-8de6f354d775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661164119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.661164119 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_lc_escalation/latest


Test location /workspace/coverage/default/5.kmac_long_msg_and_output.1737814191
Short name T1031
Test name
Test status
Simulation time 4927119033 ps
CPU time 263.07 seconds
Started Feb 25 01:55:39 PM PST 24
Finished Feb 25 02:00:03 PM PST 24
Peak memory 245048 kb
Host smart-10644862-7449-4bdf-8789-6c5c5f3bc381
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737814191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_an
d_output.1737814191 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/5.kmac_mubi.1944102535
Short name T52
Test name
Test status
Simulation time 9947143411 ps
CPU time 318.61 seconds
Started Feb 25 01:55:58 PM PST 24
Finished Feb 25 02:01:17 PM PST 24
Peak memory 249352 kb
Host smart-3fbbbc91-e7d3-45b5-bb1f-a5b8aaed8b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944102535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.1944102535 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_mubi/latest


Test location /workspace/coverage/default/5.kmac_sideload.2417530905
Short name T978
Test name
Test status
Simulation time 97722967889 ps
CPU time 275.1 seconds
Started Feb 25 01:55:43 PM PST 24
Finished Feb 25 02:00:19 PM PST 24
Peak memory 243968 kb
Host smart-610d476e-807c-47e5-9c02-b5278f999e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417530905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.2417530905 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_sideload/latest


Test location /workspace/coverage/default/5.kmac_smoke.612671227
Short name T665
Test name
Test status
Simulation time 20161878870 ps
CPU time 84.04 seconds
Started Feb 25 01:55:38 PM PST 24
Finished Feb 25 01:57:03 PM PST 24
Peak memory 224012 kb
Host smart-b3525a43-07e5-4d32-8615-7a78c8f947df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612671227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.612671227 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_smoke/latest


Test location /workspace/coverage/default/5.kmac_stress_all.1606686052
Short name T801
Test name
Test status
Simulation time 47311294734 ps
CPU time 267.28 seconds
Started Feb 25 01:55:50 PM PST 24
Finished Feb 25 02:00:17 PM PST 24
Peak memory 257176 kb
Host smart-28ad576a-5f8f-41f3-b95d-d1ffd1b0be05
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1606686052 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.1606686052 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all/latest


Test location /workspace/coverage/default/5.kmac_test_vectors_kmac.948017176
Short name T299
Test name
Test status
Simulation time 381437172 ps
CPU time 6.35 seconds
Started Feb 25 01:55:42 PM PST 24
Finished Feb 25 01:55:48 PM PST 24
Peak memory 218396 kb
Host smart-c704cf1d-e5ec-4805-a812-436bcf6908c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948017176 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.kmac_test_vectors_kmac.948017176 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/5.kmac_test_vectors_kmac_xof.2228209989
Short name T954
Test name
Test status
Simulation time 347902574 ps
CPU time 5.84 seconds
Started Feb 25 01:55:44 PM PST 24
Finished Feb 25 01:55:50 PM PST 24
Peak memory 219604 kb
Host smart-10424c7b-fbfc-4d0f-9449-7aa5c68320e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228209989 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.kmac_test_vectors_kmac_xof.2228209989 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_224.3160353134
Short name T678
Test name
Test status
Simulation time 86356024858 ps
CPU time 2203.1 seconds
Started Feb 25 01:55:44 PM PST 24
Finished Feb 25 02:32:28 PM PST 24
Peak memory 391940 kb
Host smart-4faaf175-1bd1-4901-ae3e-69febf8d1c84
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3160353134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_224.3160353134 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_256.2085961486
Short name T628
Test name
Test status
Simulation time 257426917249 ps
CPU time 2242.38 seconds
Started Feb 25 01:55:41 PM PST 24
Finished Feb 25 02:33:04 PM PST 24
Peak memory 388152 kb
Host smart-9fc951b1-bce9-4cba-b5ac-33301ec83c99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2085961486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_256.2085961486 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_384.2532073896
Short name T343
Test name
Test status
Simulation time 149408633393 ps
CPU time 1860.6 seconds
Started Feb 25 01:55:42 PM PST 24
Finished Feb 25 02:26:43 PM PST 24
Peak memory 343800 kb
Host smart-80ab5b8f-a1de-4d03-b5eb-7f198a908214
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2532073896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_384.2532073896 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_512.912271478
Short name T227
Test name
Test status
Simulation time 10619534887 ps
CPU time 1160.42 seconds
Started Feb 25 01:55:42 PM PST 24
Finished Feb 25 02:15:03 PM PST 24
Peak memory 300200 kb
Host smart-c96584dd-243d-48c1-a0b3-1ede4b91cbd3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=912271478 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_512.912271478 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/5.kmac_test_vectors_shake_128.4053299985
Short name T482
Test name
Test status
Simulation time 1089015119844 ps
CPU time 6658.52 seconds
Started Feb 25 01:55:40 PM PST 24
Finished Feb 25 03:46:40 PM PST 24
Peak memory 665964 kb
Host smart-a2f39482-142a-4ebf-94e6-778deb417e85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4053299985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_128.4053299985 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/5.kmac_test_vectors_shake_256.2164406499
Short name T726
Test name
Test status
Simulation time 210810018359 ps
CPU time 4474.24 seconds
Started Feb 25 01:55:39 PM PST 24
Finished Feb 25 03:10:14 PM PST 24
Peak memory 572400 kb
Host smart-c3b6023a-7b31-4892-b731-ef93b9ddec39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2164406499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_256.2164406499 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/6.kmac_alert_test.4103470783
Short name T102
Test name
Test status
Simulation time 14922637 ps
CPU time 0.84 seconds
Started Feb 25 01:55:49 PM PST 24
Finished Feb 25 01:55:50 PM PST 24
Peak memory 218084 kb
Host smart-5a1733fe-1e36-40b7-a80d-15975705bd66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103470783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.4103470783 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_alert_test/latest


Test location /workspace/coverage/default/6.kmac_app.3343831895
Short name T308
Test name
Test status
Simulation time 37136268559 ps
CPU time 267.01 seconds
Started Feb 25 01:55:52 PM PST 24
Finished Feb 25 02:00:19 PM PST 24
Peak memory 247032 kb
Host smart-0106a5f2-00c2-4d73-84c0-4655f5d6c3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343831895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.3343831895 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_app/latest


Test location /workspace/coverage/default/6.kmac_app_with_partial_data.1002495563
Short name T864
Test name
Test status
Simulation time 51525424368 ps
CPU time 316.4 seconds
Started Feb 25 01:55:55 PM PST 24
Finished Feb 25 02:01:11 PM PST 24
Peak memory 249448 kb
Host smart-80b9bbe9-7277-4095-8ad6-7474452179ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002495563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.1002495563 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_app_with_partial_data/latest


Test location /workspace/coverage/default/6.kmac_burst_write.564903767
Short name T453
Test name
Test status
Simulation time 16599175909 ps
CPU time 962.29 seconds
Started Feb 25 01:55:57 PM PST 24
Finished Feb 25 02:11:59 PM PST 24
Peak memory 236048 kb
Host smart-02312304-54ac-4116-b905-5c108e5fd388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564903767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.564903767 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_burst_write/latest


Test location /workspace/coverage/default/6.kmac_edn_timeout_error.2732110029
Short name T460
Test name
Test status
Simulation time 1302376713 ps
CPU time 46.39 seconds
Started Feb 25 01:55:50 PM PST 24
Finished Feb 25 01:56:37 PM PST 24
Peak memory 236384 kb
Host smart-bb10ba54-5601-456f-81d8-957b68ccf885
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2732110029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.2732110029 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/6.kmac_entropy_mode_error.616451628
Short name T81
Test name
Test status
Simulation time 84812167 ps
CPU time 1.21 seconds
Started Feb 25 01:55:55 PM PST 24
Finished Feb 25 01:55:56 PM PST 24
Peak memory 218304 kb
Host smart-d129e340-0527-4588-b61d-a88e571b30e5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=616451628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.616451628 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/6.kmac_entropy_ready_error.2894534443
Short name T657
Test name
Test status
Simulation time 3449132223 ps
CPU time 39.66 seconds
Started Feb 25 01:55:49 PM PST 24
Finished Feb 25 01:56:29 PM PST 24
Peak memory 218612 kb
Host smart-ba4b1c13-2342-40f3-b94e-ed2b18b8fc93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894534443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.2894534443 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_ready_error/latest


Test location /workspace/coverage/default/6.kmac_entropy_refresh.508768916
Short name T210
Test name
Test status
Simulation time 2162791844 ps
CPU time 42.51 seconds
Started Feb 25 01:55:51 PM PST 24
Finished Feb 25 01:56:34 PM PST 24
Peak memory 227792 kb
Host smart-ec18135e-f868-4a25-9e40-c18ceee88afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508768916 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.508768916 +enable_masking=1 +sw_
key_masked=0
Directory /workspace/6.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/6.kmac_error.3457727235
Short name T238
Test name
Test status
Simulation time 86846769 ps
CPU time 3.81 seconds
Started Feb 25 01:55:59 PM PST 24
Finished Feb 25 01:56:02 PM PST 24
Peak memory 225632 kb
Host smart-77498891-98ce-4c72-8d79-8d96a8037105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457727235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.3457727235 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_error/latest


Test location /workspace/coverage/default/6.kmac_key_error.626571907
Short name T303
Test name
Test status
Simulation time 2956278204 ps
CPU time 4.47 seconds
Started Feb 25 01:55:51 PM PST 24
Finished Feb 25 01:55:55 PM PST 24
Peak memory 218364 kb
Host smart-b0155a47-672a-4b20-8e63-1296ea47eda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626571907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.626571907 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_key_error/latest


Test location /workspace/coverage/default/6.kmac_long_msg_and_output.2269357621
Short name T395
Test name
Test status
Simulation time 9619071148 ps
CPU time 221.75 seconds
Started Feb 25 01:55:58 PM PST 24
Finished Feb 25 01:59:40 PM PST 24
Peak memory 240552 kb
Host smart-47b15129-e0e0-4c76-8994-52dbe266c2e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269357621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_an
d_output.2269357621 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/6.kmac_mubi.344408363
Short name T570
Test name
Test status
Simulation time 956241927 ps
CPU time 63.36 seconds
Started Feb 25 01:55:56 PM PST 24
Finished Feb 25 01:56:59 PM PST 24
Peak memory 230388 kb
Host smart-e831d0dc-2642-457a-a1d1-c5b881ab0e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344408363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.344408363 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_mubi/latest


Test location /workspace/coverage/default/6.kmac_sideload.888809853
Short name T261
Test name
Test status
Simulation time 1993849305 ps
CPU time 17.38 seconds
Started Feb 25 01:55:49 PM PST 24
Finished Feb 25 01:56:06 PM PST 24
Peak memory 221784 kb
Host smart-1c4cbb08-28c3-4014-90db-377178c4794d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888809853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.888809853 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_sideload/latest


Test location /workspace/coverage/default/6.kmac_smoke.3975012885
Short name T781
Test name
Test status
Simulation time 4635589651 ps
CPU time 24.22 seconds
Started Feb 25 01:55:51 PM PST 24
Finished Feb 25 01:56:15 PM PST 24
Peak memory 223380 kb
Host smart-62f4d2a9-7e28-42eb-b947-0c0364e425e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975012885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.3975012885 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_smoke/latest


Test location /workspace/coverage/default/6.kmac_stress_all.3991824837
Short name T444
Test name
Test status
Simulation time 16515403956 ps
CPU time 358.78 seconds
Started Feb 25 01:55:55 PM PST 24
Finished Feb 25 02:01:54 PM PST 24
Peak memory 276076 kb
Host smart-1957a24a-0856-4bc8-8f2a-a50e276d690b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3991824837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.3991824837 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_stress_all/latest


Test location /workspace/coverage/default/6.kmac_stress_all_with_rand_reset.1088043488
Short name T126
Test name
Test status
Simulation time 56817743705 ps
CPU time 576.81 seconds
Started Feb 25 01:55:57 PM PST 24
Finished Feb 25 02:05:33 PM PST 24
Peak memory 271880 kb
Host smart-fb57dee3-271e-4ff5-bd35-bbad8eef6e1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1088043488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all_with_rand_reset.1088043488 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/6.kmac_test_vectors_kmac.2285223051
Short name T823
Test name
Test status
Simulation time 862106769 ps
CPU time 6.63 seconds
Started Feb 25 01:55:50 PM PST 24
Finished Feb 25 01:55:56 PM PST 24
Peak memory 219920 kb
Host smart-ee568e38-bc12-4de2-ab9d-ec51e0229d0f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285223051 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.kmac_test_vectors_kmac.2285223051 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/6.kmac_test_vectors_kmac_xof.807934856
Short name T1036
Test name
Test status
Simulation time 681794537 ps
CPU time 6.38 seconds
Started Feb 25 01:55:55 PM PST 24
Finished Feb 25 01:56:02 PM PST 24
Peak memory 219920 kb
Host smart-7a40217b-b588-44d0-a5f2-8d8e1d49eabe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807934856 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.kmac_test_vectors_kmac_xof.807934856 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_224.3006885151
Short name T190
Test name
Test status
Simulation time 137824703177 ps
CPU time 2447.82 seconds
Started Feb 25 01:55:51 PM PST 24
Finished Feb 25 02:36:39 PM PST 24
Peak memory 408916 kb
Host smart-3f90593a-59ac-4a59-a21f-8a1e37f64d06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3006885151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_224.3006885151 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_256.2748988430
Short name T677
Test name
Test status
Simulation time 367358430276 ps
CPU time 2219.24 seconds
Started Feb 25 01:55:58 PM PST 24
Finished Feb 25 02:32:58 PM PST 24
Peak memory 388832 kb
Host smart-4dee3f6f-e0e1-4efe-85f9-77b7c7590ca2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2748988430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_256.2748988430 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_384.3704278401
Short name T769
Test name
Test status
Simulation time 14468829940 ps
CPU time 1687.94 seconds
Started Feb 25 01:55:56 PM PST 24
Finished Feb 25 02:24:05 PM PST 24
Peak memory 332628 kb
Host smart-6c677b0b-46d1-46d6-bdc4-6adc4178b04b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3704278401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_384.3704278401 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_512.938494029
Short name T203
Test name
Test status
Simulation time 170597152517 ps
CPU time 1344.26 seconds
Started Feb 25 01:55:55 PM PST 24
Finished Feb 25 02:18:20 PM PST 24
Peak memory 299520 kb
Host smart-31492a24-f8ea-4692-a65b-032a985cb112
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=938494029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_512.938494029 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/6.kmac_test_vectors_shake_128.3780746192
Short name T582
Test name
Test status
Simulation time 183947963201 ps
CPU time 5722.11 seconds
Started Feb 25 01:55:58 PM PST 24
Finished Feb 25 03:31:21 PM PST 24
Peak memory 658052 kb
Host smart-e4373b1c-9349-4f33-b0a3-9dd9f2a4335f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3780746192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_128.3780746192 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/6.kmac_test_vectors_shake_256.1557393591
Short name T755
Test name
Test status
Simulation time 575245161909 ps
CPU time 5044.65 seconds
Started Feb 25 01:55:58 PM PST 24
Finished Feb 25 03:20:04 PM PST 24
Peak memory 565904 kb
Host smart-a34c4f0b-794f-4463-96f9-62a2b88668ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1557393591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_256.1557393591 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/7.kmac_alert_test.1166785279
Short name T825
Test name
Test status
Simulation time 26412935 ps
CPU time 0.81 seconds
Started Feb 25 01:56:08 PM PST 24
Finished Feb 25 01:56:09 PM PST 24
Peak memory 218084 kb
Host smart-29352118-80b7-45b3-993b-ad252ffec594
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166785279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.1166785279 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_alert_test/latest


Test location /workspace/coverage/default/7.kmac_app.2992289876
Short name T944
Test name
Test status
Simulation time 1674747791 ps
CPU time 10.45 seconds
Started Feb 25 01:56:07 PM PST 24
Finished Feb 25 01:56:18 PM PST 24
Peak memory 221516 kb
Host smart-d0819584-9a55-4341-8a01-2dfe7b2dd6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992289876 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.2992289876 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_app/latest


Test location /workspace/coverage/default/7.kmac_app_with_partial_data.4037607486
Short name T135
Test name
Test status
Simulation time 11199141845 ps
CPU time 129.07 seconds
Started Feb 25 01:56:09 PM PST 24
Finished Feb 25 01:58:18 PM PST 24
Peak memory 243028 kb
Host smart-a29f0086-9b3f-4945-a81f-444832375376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037607486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.4037607486 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_app_with_partial_data/latest


Test location /workspace/coverage/default/7.kmac_burst_write.3295695799
Short name T248
Test name
Test status
Simulation time 18550868231 ps
CPU time 1028.19 seconds
Started Feb 25 01:56:09 PM PST 24
Finished Feb 25 02:13:17 PM PST 24
Peak memory 242976 kb
Host smart-9bf7c037-b815-4b25-a853-0a37a00addd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295695799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.3295695799 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_burst_write/latest


Test location /workspace/coverage/default/7.kmac_edn_timeout_error.93703436
Short name T902
Test name
Test status
Simulation time 978433570 ps
CPU time 34.66 seconds
Started Feb 25 01:56:10 PM PST 24
Finished Feb 25 01:56:45 PM PST 24
Peak memory 227932 kb
Host smart-f250eb38-1fa5-4523-a896-9e730bc4c87b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=93703436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.93703436 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/7.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/7.kmac_entropy_mode_error.3078753377
Short name T82
Test name
Test status
Simulation time 18097553 ps
CPU time 0.96 seconds
Started Feb 25 01:56:11 PM PST 24
Finished Feb 25 01:56:12 PM PST 24
Peak memory 218024 kb
Host smart-588aa2e9-506a-44be-96fc-8e52efb15348
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3078753377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.3078753377 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/7.kmac_entropy_ready_error.1632417612
Short name T367
Test name
Test status
Simulation time 28418777287 ps
CPU time 72.76 seconds
Started Feb 25 01:56:07 PM PST 24
Finished Feb 25 01:57:20 PM PST 24
Peak memory 222228 kb
Host smart-a34d4ef0-c03c-4c99-a266-4c00b360a24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632417612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.1632417612 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_ready_error/latest


Test location /workspace/coverage/default/7.kmac_entropy_refresh.1786968256
Short name T723
Test name
Test status
Simulation time 53366026701 ps
CPU time 400.1 seconds
Started Feb 25 01:56:13 PM PST 24
Finished Feb 25 02:02:54 PM PST 24
Peak memory 253228 kb
Host smart-7909b7e2-f44c-4e6c-aacd-29aeacea0ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786968256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.1786968256 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/7.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/7.kmac_error.139349491
Short name T298
Test name
Test status
Simulation time 101411110438 ps
CPU time 238.44 seconds
Started Feb 25 01:56:09 PM PST 24
Finished Feb 25 02:00:07 PM PST 24
Peak memory 251432 kb
Host smart-ffc4cdca-3e39-4b5e-9c0d-d365ee02d672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139349491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.139349491 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_error/latest


Test location /workspace/coverage/default/7.kmac_key_error.1949263692
Short name T105
Test name
Test status
Simulation time 900386854 ps
CPU time 6.48 seconds
Started Feb 25 01:56:10 PM PST 24
Finished Feb 25 01:56:17 PM PST 24
Peak memory 218416 kb
Host smart-d14e5b0d-282c-4be5-9398-07851ff57a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949263692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.1949263692 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_key_error/latest


Test location /workspace/coverage/default/7.kmac_lc_escalation.2882308104
Short name T691
Test name
Test status
Simulation time 30341611 ps
CPU time 1.36 seconds
Started Feb 25 01:56:14 PM PST 24
Finished Feb 25 01:56:15 PM PST 24
Peak memory 219368 kb
Host smart-325b4e7d-a245-42aa-b881-b3a75be2713c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882308104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.2882308104 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/7.kmac_lc_escalation/latest


Test location /workspace/coverage/default/7.kmac_long_msg_and_output.2115527904
Short name T592
Test name
Test status
Simulation time 103377383478 ps
CPU time 1933.43 seconds
Started Feb 25 01:56:06 PM PST 24
Finished Feb 25 02:28:19 PM PST 24
Peak memory 376108 kb
Host smart-d5927e27-e5ce-4da7-a240-bbf0f05decbc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115527904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_an
d_output.2115527904 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/7.kmac_mubi.3295156397
Short name T518
Test name
Test status
Simulation time 3263732199 ps
CPU time 84.13 seconds
Started Feb 25 01:56:11 PM PST 24
Finished Feb 25 01:57:35 PM PST 24
Peak memory 243316 kb
Host smart-c0e62ef6-0620-4138-add7-ae374d28dd1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295156397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.3295156397 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_mubi/latest


Test location /workspace/coverage/default/7.kmac_sideload.4078326789
Short name T612
Test name
Test status
Simulation time 18532585571 ps
CPU time 480.15 seconds
Started Feb 25 01:56:10 PM PST 24
Finished Feb 25 02:04:10 PM PST 24
Peak memory 256252 kb
Host smart-9caccce3-4e2d-4e6c-a5a3-028f5f5da630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078326789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.4078326789 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_sideload/latest


Test location /workspace/coverage/default/7.kmac_smoke.3795103211
Short name T466
Test name
Test status
Simulation time 14523209052 ps
CPU time 82.58 seconds
Started Feb 25 01:55:50 PM PST 24
Finished Feb 25 01:57:12 PM PST 24
Peak memory 226616 kb
Host smart-ccfbb905-69fb-4434-9cfe-a7b3d66ba337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795103211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.3795103211 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_smoke/latest


Test location /workspace/coverage/default/7.kmac_stress_all.2895400021
Short name T947
Test name
Test status
Simulation time 250490738622 ps
CPU time 2214.33 seconds
Started Feb 25 01:56:13 PM PST 24
Finished Feb 25 02:33:08 PM PST 24
Peak memory 431592 kb
Host smart-332017d3-3cee-4107-a8c2-4393255e6ed3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2895400021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.2895400021 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all/latest


Test location /workspace/coverage/default/7.kmac_test_vectors_kmac.3659751801
Short name T468
Test name
Test status
Simulation time 825363986 ps
CPU time 6.17 seconds
Started Feb 25 01:56:08 PM PST 24
Finished Feb 25 01:56:14 PM PST 24
Peak memory 219812 kb
Host smart-4f6e50c7-8276-4536-b00e-f5591095e071
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659751801 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.kmac_test_vectors_kmac.3659751801 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/7.kmac_test_vectors_kmac_xof.4210483784
Short name T436
Test name
Test status
Simulation time 847574977 ps
CPU time 6.44 seconds
Started Feb 25 01:56:06 PM PST 24
Finished Feb 25 01:56:13 PM PST 24
Peak memory 218476 kb
Host smart-575f72f0-35f6-461a-be24-b2d15f724a79
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210483784 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.kmac_test_vectors_kmac_xof.4210483784 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_224.1869622050
Short name T241
Test name
Test status
Simulation time 31127345177 ps
CPU time 2038.51 seconds
Started Feb 25 01:56:10 PM PST 24
Finished Feb 25 02:30:08 PM PST 24
Peak memory 407808 kb
Host smart-07d01fa3-31da-4d86-a1e0-086ab4639c8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1869622050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_224.1869622050 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_256.3776857724
Short name T1018
Test name
Test status
Simulation time 80557987836 ps
CPU time 2086.07 seconds
Started Feb 25 01:56:06 PM PST 24
Finished Feb 25 02:30:53 PM PST 24
Peak memory 379888 kb
Host smart-6b6fdae8-08a0-451d-a8db-a8d18784f57c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3776857724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_256.3776857724 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_384.3946506527
Short name T734
Test name
Test status
Simulation time 50264162739 ps
CPU time 1450.12 seconds
Started Feb 25 01:56:08 PM PST 24
Finished Feb 25 02:20:18 PM PST 24
Peak memory 337600 kb
Host smart-0571b1f6-0c44-4208-b8cf-c1d053a57d70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3946506527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_384.3946506527 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_512.1081151429
Short name T254
Test name
Test status
Simulation time 49614512530 ps
CPU time 1347.52 seconds
Started Feb 25 01:56:13 PM PST 24
Finished Feb 25 02:18:41 PM PST 24
Peak memory 297084 kb
Host smart-6e400dc6-cd53-4b2b-9f67-227cf27c3656
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1081151429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_512.1081151429 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/7.kmac_test_vectors_shake_128.1027437342
Short name T840
Test name
Test status
Simulation time 1301855296447 ps
CPU time 6795.52 seconds
Started Feb 25 01:56:07 PM PST 24
Finished Feb 25 03:49:24 PM PST 24
Peak memory 661144 kb
Host smart-11683013-2dfc-4949-9d69-60bf24e758d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1027437342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_128.1027437342 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/7.kmac_test_vectors_shake_256.1098245847
Short name T873
Test name
Test status
Simulation time 108367347814 ps
CPU time 4755.44 seconds
Started Feb 25 01:56:13 PM PST 24
Finished Feb 25 03:15:29 PM PST 24
Peak memory 588736 kb
Host smart-3ca6a93b-829d-4415-a950-f15249902447
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1098245847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_256.1098245847 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/8.kmac_alert_test.4197754186
Short name T501
Test name
Test status
Simulation time 17148839 ps
CPU time 0.83 seconds
Started Feb 25 01:56:10 PM PST 24
Finished Feb 25 01:56:10 PM PST 24
Peak memory 219312 kb
Host smart-8ea93121-fd31-4c16-8d83-7ec49fbe506e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197754186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.4197754186 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_alert_test/latest


Test location /workspace/coverage/default/8.kmac_app.2232063331
Short name T484
Test name
Test status
Simulation time 5496226485 ps
CPU time 402.62 seconds
Started Feb 25 01:56:13 PM PST 24
Finished Feb 25 02:02:56 PM PST 24
Peak memory 256320 kb
Host smart-5ab3ec3c-872a-4928-a8eb-2ba0a1a4361b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232063331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.2232063331 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_app/latest


Test location /workspace/coverage/default/8.kmac_app_with_partial_data.2525776840
Short name T1022
Test name
Test status
Simulation time 14843071314 ps
CPU time 421.87 seconds
Started Feb 25 01:56:10 PM PST 24
Finished Feb 25 02:03:11 PM PST 24
Peak memory 256152 kb
Host smart-fc65bcc5-c217-4a12-bb8a-74a4d20b2679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525776840 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.2525776840 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_app_with_partial_data/latest


Test location /workspace/coverage/default/8.kmac_burst_write.3713166088
Short name T861
Test name
Test status
Simulation time 23842721004 ps
CPU time 1235.22 seconds
Started Feb 25 01:56:06 PM PST 24
Finished Feb 25 02:16:42 PM PST 24
Peak memory 238776 kb
Host smart-674d5940-a4c8-47c5-b940-6401a02b014e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713166088 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.3713166088 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_burst_write/latest


Test location /workspace/coverage/default/8.kmac_edn_timeout_error.2393627451
Short name T959
Test name
Test status
Simulation time 28209433 ps
CPU time 1.19 seconds
Started Feb 25 01:56:09 PM PST 24
Finished Feb 25 01:56:10 PM PST 24
Peak memory 218284 kb
Host smart-e682f93e-411b-4efe-af3e-447d4a5a31c7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2393627451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.2393627451 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/8.kmac_entropy_mode_error.3142763450
Short name T376
Test name
Test status
Simulation time 86791287 ps
CPU time 1.09 seconds
Started Feb 25 01:56:13 PM PST 24
Finished Feb 25 01:56:15 PM PST 24
Peak memory 218144 kb
Host smart-c594ca07-b345-4d06-9b56-9d85191e270a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3142763450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.3142763450 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/8.kmac_entropy_ready_error.3632401014
Short name T626
Test name
Test status
Simulation time 14891903660 ps
CPU time 37.06 seconds
Started Feb 25 01:56:09 PM PST 24
Finished Feb 25 01:56:46 PM PST 24
Peak memory 219328 kb
Host smart-c7754eb3-bab1-435f-a190-65d8336ce89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632401014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.3632401014 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_ready_error/latest


Test location /workspace/coverage/default/8.kmac_entropy_refresh.1995912912
Short name T859
Test name
Test status
Simulation time 62218803912 ps
CPU time 183.87 seconds
Started Feb 25 01:56:10 PM PST 24
Finished Feb 25 01:59:14 PM PST 24
Peak memory 242852 kb
Host smart-d90cd378-296f-4aa3-b88c-677a42d6d11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995912912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.1995912912 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/8.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/8.kmac_key_error.255781316
Short name T763
Test name
Test status
Simulation time 3665316101 ps
CPU time 2.97 seconds
Started Feb 25 01:56:08 PM PST 24
Finished Feb 25 01:56:11 PM PST 24
Peak memory 218428 kb
Host smart-259b09c3-0c93-43e7-9998-1dea9635b93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255781316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.255781316 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_key_error/latest


Test location /workspace/coverage/default/8.kmac_lc_escalation.1825194029
Short name T50
Test name
Test status
Simulation time 641289874 ps
CPU time 32.63 seconds
Started Feb 25 01:56:07 PM PST 24
Finished Feb 25 01:56:40 PM PST 24
Peak memory 236372 kb
Host smart-ea7f0372-3ea3-40a6-85a4-7d3d3afb5b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825194029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.1825194029 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/8.kmac_lc_escalation/latest


Test location /workspace/coverage/default/8.kmac_long_msg_and_output.3362358208
Short name T257
Test name
Test status
Simulation time 192303579551 ps
CPU time 1034.09 seconds
Started Feb 25 01:56:10 PM PST 24
Finished Feb 25 02:13:25 PM PST 24
Peak memory 295572 kb
Host smart-c05f25b3-6af3-4a2c-a866-f48e5feb86e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362358208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_an
d_output.3362358208 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/8.kmac_mubi.3396033084
Short name T58
Test name
Test status
Simulation time 53208050018 ps
CPU time 372.04 seconds
Started Feb 25 01:56:08 PM PST 24
Finished Feb 25 02:02:20 PM PST 24
Peak memory 254632 kb
Host smart-8e1823cc-6c3a-4cd1-a24e-ef83bcf00917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396033084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.3396033084 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_mubi/latest


Test location /workspace/coverage/default/8.kmac_sideload.886433559
Short name T681
Test name
Test status
Simulation time 26602573507 ps
CPU time 224.62 seconds
Started Feb 25 01:56:08 PM PST 24
Finished Feb 25 01:59:53 PM PST 24
Peak memory 241604 kb
Host smart-b6b18f53-64e4-4951-91fc-98c169e0e47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886433559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.886433559 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_sideload/latest


Test location /workspace/coverage/default/8.kmac_smoke.396261993
Short name T935
Test name
Test status
Simulation time 123022448 ps
CPU time 2.87 seconds
Started Feb 25 01:56:11 PM PST 24
Finished Feb 25 01:56:14 PM PST 24
Peak memory 218524 kb
Host smart-31a30c73-3fd8-489a-bb10-5c4b598ecee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396261993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.396261993 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_smoke/latest


Test location /workspace/coverage/default/8.kmac_stress_all.1725947864
Short name T1029
Test name
Test status
Simulation time 12939753152 ps
CPU time 313.16 seconds
Started Feb 25 01:56:12 PM PST 24
Finished Feb 25 02:01:25 PM PST 24
Peak memory 260644 kb
Host smart-29a70373-35be-4044-af10-075aa5ea901e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1725947864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.1725947864 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_stress_all/latest


Test location /workspace/coverage/default/8.kmac_stress_all_with_rand_reset.2104140135
Short name T150
Test name
Test status
Simulation time 318389343019 ps
CPU time 1150.73 seconds
Started Feb 25 01:56:08 PM PST 24
Finished Feb 25 02:15:19 PM PST 24
Peak memory 281528 kb
Host smart-0c0cb44a-feda-4f08-b6d5-cc69d6491dbb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2104140135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all_with_rand_reset.2104140135 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/8.kmac_test_vectors_kmac.2227083125
Short name T383
Test name
Test status
Simulation time 966465566 ps
CPU time 6.81 seconds
Started Feb 25 01:56:09 PM PST 24
Finished Feb 25 01:56:16 PM PST 24
Peak memory 218432 kb
Host smart-8b1e6956-aefc-468e-9fb3-a516d3406295
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227083125 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.kmac_test_vectors_kmac.2227083125 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/8.kmac_test_vectors_kmac_xof.3711357363
Short name T274
Test name
Test status
Simulation time 202308761 ps
CPU time 6.89 seconds
Started Feb 25 01:56:08 PM PST 24
Finished Feb 25 01:56:15 PM PST 24
Peak memory 218340 kb
Host smart-9df46253-4717-4f41-9682-7914313e6290
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711357363 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.kmac_test_vectors_kmac_xof.3711357363 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_224.547463234
Short name T351
Test name
Test status
Simulation time 65848831555 ps
CPU time 2278.02 seconds
Started Feb 25 01:56:10 PM PST 24
Finished Feb 25 02:34:09 PM PST 24
Peak memory 400992 kb
Host smart-b9bd5e93-278c-44fd-8ee9-86865797ce17
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=547463234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_224.547463234 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_256.2649121460
Short name T534
Test name
Test status
Simulation time 345765674085 ps
CPU time 2264.53 seconds
Started Feb 25 01:56:13 PM PST 24
Finished Feb 25 02:33:57 PM PST 24
Peak memory 385424 kb
Host smart-fab9bdf2-e543-4599-9119-7019ea7d54c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2649121460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_256.2649121460 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_384.3723056077
Short name T480
Test name
Test status
Simulation time 96124055687 ps
CPU time 1764.06 seconds
Started Feb 25 01:56:08 PM PST 24
Finished Feb 25 02:25:32 PM PST 24
Peak memory 343472 kb
Host smart-7d04e101-b931-4e34-9a4b-0f9b2970018f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3723056077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_384.3723056077 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_512.2928370554
Short name T727
Test name
Test status
Simulation time 133065266788 ps
CPU time 1326.88 seconds
Started Feb 25 01:56:12 PM PST 24
Finished Feb 25 02:18:19 PM PST 24
Peak memory 299944 kb
Host smart-7006e3df-e921-4fc5-a6bb-40912577e551
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2928370554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_512.2928370554 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/8.kmac_test_vectors_shake_128.2642312171
Short name T711
Test name
Test status
Simulation time 1034005038114 ps
CPU time 6293.96 seconds
Started Feb 25 01:56:10 PM PST 24
Finished Feb 25 03:41:04 PM PST 24
Peak memory 658424 kb
Host smart-6214e3b2-78f7-413e-bcff-fd93e197d4aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2642312171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_128.2642312171 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/8.kmac_test_vectors_shake_256.1226979129
Short name T718
Test name
Test status
Simulation time 603708934885 ps
CPU time 5062.07 seconds
Started Feb 25 01:56:08 PM PST 24
Finished Feb 25 03:20:31 PM PST 24
Peak memory 576216 kb
Host smart-efc7c098-7c3f-47f9-8b04-8460047bdae7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1226979129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_256.1226979129 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/9.kmac_alert_test.731151914
Short name T408
Test name
Test status
Simulation time 50128757 ps
CPU time 0.9 seconds
Started Feb 25 01:56:15 PM PST 24
Finished Feb 25 01:56:16 PM PST 24
Peak memory 218024 kb
Host smart-0da0cbda-1a4c-4a9a-9d8f-0223da8a15f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731151914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.731151914 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/9.kmac_alert_test/latest


Test location /workspace/coverage/default/9.kmac_app.2505719698
Short name T1063
Test name
Test status
Simulation time 751778797 ps
CPU time 19.13 seconds
Started Feb 25 01:56:19 PM PST 24
Finished Feb 25 01:56:38 PM PST 24
Peak memory 228364 kb
Host smart-386a690a-6ac7-4576-9cf5-4c68323cf2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505719698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.2505719698 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_app/latest


Test location /workspace/coverage/default/9.kmac_app_with_partial_data.1768912069
Short name T306
Test name
Test status
Simulation time 8282458163 ps
CPU time 96.12 seconds
Started Feb 25 01:56:14 PM PST 24
Finished Feb 25 01:57:50 PM PST 24
Peak memory 233520 kb
Host smart-dba08236-c90b-408a-b232-39331341bf8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768912069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.1768912069 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_app_with_partial_data/latest


Test location /workspace/coverage/default/9.kmac_burst_write.2989788186
Short name T742
Test name
Test status
Simulation time 69442082148 ps
CPU time 668.13 seconds
Started Feb 25 01:56:19 PM PST 24
Finished Feb 25 02:07:27 PM PST 24
Peak memory 235340 kb
Host smart-6bc2fed7-cab8-4969-8bc8-44463c11bcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989788186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.2989788186 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_burst_write/latest


Test location /workspace/coverage/default/9.kmac_edn_timeout_error.374041910
Short name T72
Test name
Test status
Simulation time 30913514 ps
CPU time 1.23 seconds
Started Feb 25 01:56:17 PM PST 24
Finished Feb 25 01:56:18 PM PST 24
Peak memory 218328 kb
Host smart-52bba5f4-12ad-403f-befd-07f168c181e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=374041910 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.374041910 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/9.kmac_entropy_mode_error.1798558893
Short name T471
Test name
Test status
Simulation time 135955870 ps
CPU time 1.18 seconds
Started Feb 25 01:56:15 PM PST 24
Finished Feb 25 01:56:16 PM PST 24
Peak memory 218008 kb
Host smart-1b3a732f-5f7e-4cfd-b720-bcb057025f74
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1798558893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.1798558893 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/9.kmac_entropy_ready_error.3333066199
Short name T40
Test name
Test status
Simulation time 7010308943 ps
CPU time 58.82 seconds
Started Feb 25 01:56:14 PM PST 24
Finished Feb 25 01:57:13 PM PST 24
Peak memory 221108 kb
Host smart-4e588c32-02fd-43f0-bd3f-c9718499d90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333066199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.3333066199 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_ready_error/latest


Test location /workspace/coverage/default/9.kmac_entropy_refresh.4216514510
Short name T705
Test name
Test status
Simulation time 28796531982 ps
CPU time 391.17 seconds
Started Feb 25 01:56:16 PM PST 24
Finished Feb 25 02:02:47 PM PST 24
Peak memory 254596 kb
Host smart-c2dd5f61-d894-428d-a96b-aced790369b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216514510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.4216514510 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/9.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/9.kmac_error.2523994906
Short name T573
Test name
Test status
Simulation time 25792927249 ps
CPU time 333.91 seconds
Started Feb 25 01:56:16 PM PST 24
Finished Feb 25 02:01:50 PM PST 24
Peak memory 259076 kb
Host smart-451f0487-78f8-401e-9de9-16a82d75ac34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523994906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.2523994906 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_error/latest


Test location /workspace/coverage/default/9.kmac_key_error.4165722994
Short name T259
Test name
Test status
Simulation time 4450181785 ps
CPU time 7.5 seconds
Started Feb 25 01:56:17 PM PST 24
Finished Feb 25 01:56:24 PM PST 24
Peak memory 218420 kb
Host smart-f940f80d-1eff-4fa2-8877-9e52c7deba3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165722994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.4165722994 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_key_error/latest


Test location /workspace/coverage/default/9.kmac_lc_escalation.2409630482
Short name T887
Test name
Test status
Simulation time 143034514 ps
CPU time 1.46 seconds
Started Feb 25 01:56:14 PM PST 24
Finished Feb 25 01:56:15 PM PST 24
Peak memory 219272 kb
Host smart-7083b202-5dab-44f9-8569-cedbb19f65d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409630482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.2409630482 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/9.kmac_lc_escalation/latest


Test location /workspace/coverage/default/9.kmac_long_msg_and_output.3894045710
Short name T766
Test name
Test status
Simulation time 2375027033 ps
CPU time 79.54 seconds
Started Feb 25 01:56:16 PM PST 24
Finished Feb 25 01:57:36 PM PST 24
Peak memory 235772 kb
Host smart-9bf8e955-8cae-4b6b-a6f3-2f800b394ab4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894045710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_an
d_output.3894045710 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/9.kmac_mubi.3400860638
Short name T593
Test name
Test status
Simulation time 2895224632 ps
CPU time 42.67 seconds
Started Feb 25 01:56:14 PM PST 24
Finished Feb 25 01:56:57 PM PST 24
Peak memory 228208 kb
Host smart-2c622eb4-fb4d-4b71-a8fe-7accfa46e317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400860638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.3400860638 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_mubi/latest


Test location /workspace/coverage/default/9.kmac_sideload.2256553041
Short name T798
Test name
Test status
Simulation time 3272391260 ps
CPU time 291.19 seconds
Started Feb 25 01:56:17 PM PST 24
Finished Feb 25 02:01:08 PM PST 24
Peak memory 244024 kb
Host smart-d05214ab-f0ae-4a22-b1e9-693560fe12d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256553041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.2256553041 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_sideload/latest


Test location /workspace/coverage/default/9.kmac_smoke.1750146077
Short name T1070
Test name
Test status
Simulation time 6007905262 ps
CPU time 40.26 seconds
Started Feb 25 01:56:13 PM PST 24
Finished Feb 25 01:56:54 PM PST 24
Peak memory 226464 kb
Host smart-ff668a44-1afa-4551-a1d2-46daccbe62e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750146077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.1750146077 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_smoke/latest


Test location /workspace/coverage/default/9.kmac_stress_all.1089232948
Short name T145
Test name
Test status
Simulation time 7181636687 ps
CPU time 335.05 seconds
Started Feb 25 01:56:16 PM PST 24
Finished Feb 25 02:01:52 PM PST 24
Peak memory 233292 kb
Host smart-ba466f19-20ef-4290-906e-155c0345c800
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1089232948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.1089232948 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_stress_all/latest


Test location /workspace/coverage/default/9.kmac_stress_all_with_rand_reset.1505928788
Short name T128
Test name
Test status
Simulation time 82294643973 ps
CPU time 1706 seconds
Started Feb 25 01:56:15 PM PST 24
Finished Feb 25 02:24:41 PM PST 24
Peak memory 350940 kb
Host smart-9b60dbb3-44f2-4b94-9f50-c61ba9d1893f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1505928788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all_with_rand_reset.1505928788 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/9.kmac_test_vectors_kmac.574021251
Short name T258
Test name
Test status
Simulation time 220312793 ps
CPU time 5.66 seconds
Started Feb 25 01:56:17 PM PST 24
Finished Feb 25 01:56:23 PM PST 24
Peak memory 218388 kb
Host smart-d5303be8-1c11-4bb6-8522-1a5e1c6f83bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574021251 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.kmac_test_vectors_kmac.574021251 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/9.kmac_test_vectors_kmac_xof.515853317
Short name T1069
Test name
Test status
Simulation time 245606718 ps
CPU time 6.46 seconds
Started Feb 25 01:56:17 PM PST 24
Finished Feb 25 01:56:24 PM PST 24
Peak memory 219680 kb
Host smart-d49f182f-9402-4a99-950b-e57612f41faf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515853317 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.kmac_test_vectors_kmac_xof.515853317 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_224.1851842512
Short name T961
Test name
Test status
Simulation time 127807603624 ps
CPU time 2387.8 seconds
Started Feb 25 01:56:11 PM PST 24
Finished Feb 25 02:36:00 PM PST 24
Peak memory 398168 kb
Host smart-c8b9ba8d-d780-4d28-ba2a-841633eeca88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1851842512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_224.1851842512 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_256.1546769881
Short name T908
Test name
Test status
Simulation time 121759899377 ps
CPU time 2165.68 seconds
Started Feb 25 01:56:14 PM PST 24
Finished Feb 25 02:32:20 PM PST 24
Peak memory 391568 kb
Host smart-938272ab-c24a-4e88-ae04-0570775afb61
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1546769881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_256.1546769881 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_384.101191925
Short name T987
Test name
Test status
Simulation time 15172287971 ps
CPU time 1536.57 seconds
Started Feb 25 01:56:14 PM PST 24
Finished Feb 25 02:21:51 PM PST 24
Peak memory 337724 kb
Host smart-1caa457a-a3e4-48f2-8d10-d942ebcdb4fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=101191925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_384.101191925 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_512.1360452064
Short name T1068
Test name
Test status
Simulation time 21619558824 ps
CPU time 1200.8 seconds
Started Feb 25 01:56:14 PM PST 24
Finished Feb 25 02:16:15 PM PST 24
Peak memory 298120 kb
Host smart-5d098479-c1b8-4d11-819a-87af7a02a106
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1360452064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_512.1360452064 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/9.kmac_test_vectors_shake_128.1588762172
Short name T1016
Test name
Test status
Simulation time 723817138483 ps
CPU time 5782.09 seconds
Started Feb 25 01:56:18 PM PST 24
Finished Feb 25 03:32:41 PM PST 24
Peak memory 634760 kb
Host smart-adfa7a6b-0adc-445d-a82c-f9732cde35c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1588762172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_128.1588762172 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/9.kmac_test_vectors_shake_256.1363373054
Short name T481
Test name
Test status
Simulation time 597234445447 ps
CPU time 4964.2 seconds
Started Feb 25 01:56:15 PM PST 24
Finished Feb 25 03:19:00 PM PST 24
Peak memory 568820 kb
Host smart-90158707-e96e-4ae5-821a-0a4a6ab4c7bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1363373054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_256.1363373054 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_256/latest
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