Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100600291	1			T1	160793		T3	223821		T7	292
all_values[1]	100600291	1			T1	160793		T3	223821		T7	292
all_values[2]	100600291	1			T1	160793		T3	223821		T7	292

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

575894

1

T1

8269

T3

8031

T7

6

auto[1]

301224979

1

T1

474110

T3

663432

T7

870

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300272925

1

T1

480867

T3

670815

T7

840

auto[1]

1527948

1

T1

1512

T3

648

T7

36

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	185504	1			T1	2892		T3	1233		T29	326
all_values[0]	auto[0]	auto[1]	2147	1			T1	10		T3	2		T29	4
all_values[0]	auto[1]	auto[0]	99905471	1			T1	157397		T3	222372		T7	280
all_values[0]	auto[1]	auto[1]	507169	1			T1	494		T3	214		T7	12
all_values[1]	auto[0]	auto[0]	172832	1			T1	5300		T3	5557		T28	4550
all_values[1]	auto[0]	auto[1]	1560	1			T1	7		T3	4		T28	3
all_values[1]	auto[1]	auto[0]	99918143	1			T1	154989		T3	218048		T7	280
all_values[1]	auto[1]	auto[1]	507756	1			T1	497		T3	212		T7	12
all_values[2]	auto[0]	auto[0]	212242	1			T1	55		T3	1233		T7	5
all_values[2]	auto[0]	auto[1]	1609	1			T1	5		T3	2		T7	1
all_values[2]	auto[1]	auto[0]	99878733	1			T1	160234		T3	222372		T7	275
all_values[2]	auto[1]	auto[1]	507707	1			T1	499		T3	214		T7	11