Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
329000 |
1 |
|
|
T1 |
334 |
|
T3 |
2 |
|
T7 |
2 |
auto[1] |
364276 |
1 |
|
|
T1 |
442 |
|
T3 |
278 |
|
T7 |
16 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173213 |
1 |
|
|
T1 |
178 |
|
T3 |
53 |
|
T7 |
2 |
lower_val |
171682 |
1 |
|
|
T1 |
203 |
|
T3 |
90 |
|
T7 |
4 |
zero_val |
1917 |
1 |
|
|
T1 |
11 |
|
T3 |
1 |
|
T7 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
254194 |
1 |
|
|
T1 |
242 |
|
T3 |
62 |
|
T7 |
4 |
lower_val |
256286 |
1 |
|
|
T1 |
288 |
|
T3 |
72 |
|
T7 |
4 |
zero_val |
182796 |
1 |
|
|
T1 |
246 |
|
T3 |
146 |
|
T7 |
10 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
40518 |
1 |
|
|
T1 |
24 |
|
T29 |
26 |
|
T31 |
3 |
higher_val |
higher_val |
auto[1] |
22453 |
1 |
|
|
T1 |
19 |
|
T3 |
12 |
|
T7 |
1 |
higher_val |
lower_val |
auto[0] |
41319 |
1 |
|
|
T1 |
37 |
|
T29 |
36 |
|
T31 |
3 |
higher_val |
lower_val |
auto[1] |
23031 |
1 |
|
|
T1 |
36 |
|
T3 |
16 |
|
T28 |
24 |
higher_val |
zero_val |
auto[0] |
97 |
1 |
|
|
T1 |
1 |
|
T190 |
1 |
|
T191 |
1 |
higher_val |
zero_val |
auto[1] |
45795 |
1 |
|
|
T1 |
61 |
|
T3 |
25 |
|
T7 |
1 |
lower_val |
higher_val |
auto[0] |
40498 |
1 |
|
|
T1 |
46 |
|
T7 |
1 |
|
T29 |
43 |
lower_val |
higher_val |
auto[1] |
22386 |
1 |
|
|
T1 |
23 |
|
T3 |
22 |
|
T28 |
31 |
lower_val |
lower_val |
auto[0] |
40802 |
1 |
|
|
T1 |
51 |
|
T29 |
35 |
|
T31 |
3 |
lower_val |
lower_val |
auto[1] |
22810 |
1 |
|
|
T1 |
24 |
|
T3 |
23 |
|
T7 |
2 |
lower_val |
zero_val |
auto[0] |
96 |
1 |
|
|
T28 |
1 |
|
T30 |
1 |
|
T22 |
1 |
lower_val |
zero_val |
auto[1] |
45090 |
1 |
|
|
T1 |
59 |
|
T3 |
45 |
|
T7 |
1 |
zero_val |
higher_val |
auto[0] |
553 |
1 |
|
|
T1 |
1 |
|
T7 |
1 |
|
T29 |
1 |
zero_val |
higher_val |
auto[1] |
162 |
1 |
|
|
T1 |
1 |
|
T71 |
1 |
|
T192 |
1 |
zero_val |
lower_val |
auto[0] |
509 |
1 |
|
|
T1 |
2 |
|
T32 |
1 |
|
T8 |
1 |
zero_val |
lower_val |
auto[1] |
150 |
1 |
|
|
T1 |
1 |
|
T87 |
1 |
|
T9 |
1 |
zero_val |
zero_val |
auto[0] |
307 |
1 |
|
|
T1 |
2 |
|
T3 |
1 |
|
T28 |
1 |
zero_val |
zero_val |
auto[1] |
236 |
1 |
|
|
T1 |
4 |
|
T87 |
1 |
|
T9 |
1 |