Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

Group : kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

---

Summary for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hash_mode	3	0	3	100.00	100	1	1	0
kmac_mode	2	0	2	100.00	100	1	1	2
msgfifo_depth	11	0	11	100.00	100	1	1	0
msgfifo_empty	2	0	2	100.00	100	1	1	2
msgfifo_full	2	0	2	100.00	100	1	1	2

Summary for Variable hash_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for hash_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
cshake	17281247	1			T1	183448		T3	184793		T7	273
shake	57350825	1			T1	70532		T3	61944		T28	48984
sha3	35514434	1			T1	2711		T3	2307		T28	1712

---

Summary for Variable kmac_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_mode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

92864111

1

T1

73233

T3

64251

T28

50696

auto[1]

17282395

1

T1

183458

T3

184793

T7

273

---

Summary for Variable msgfifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for msgfifo_depth

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
depth[0x00]	92731398	1			T1	163887		T3	190768		T7	245
depth[0x01]	3843358	1			T1	12526		T3	12100		T7	15
depth[0x02]	3419328	1			T1	14989		T3	12624		T7	7
depth[0x03]	3195084	1			T1	14791		T3	12227		T7	4
depth[0x04]	2843501	1			T1	12973		T3	11262		T7	2
depth[0x05]	1627676	1			T1	9767		T3	6231		T29	657
depth[0x06]	500406	1			T1	5154		T3	1246		T29	234
depth[0x07]	411194	1			T1	4460		T3	214		T29	229
depth[0x08]	404283	1			T1	4508		T3	276		T29	285
depth[0x09]	382827	1			T1	4418		T3	192		T29	230
depth[0x0a]	787451	1			T1	9218		T3	1904		T29	1676

---

Summary for Variable msgfifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msgfifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17415108

1

T1

92804

T3

58276

T7

28

auto[1]

92731398

1

T1

163887

T3

190768

T7

245

---

Summary for Variable msgfifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msgfifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

109359055

1

T1

247473

T3

247140

T7

273

auto[1]

787451

1

T1

9218

T3

1904

T29

1676