Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100600291	1			T1	160793		T3	223821		T7	292
all_pins[1]	100600291	1			T1	160793		T3	223821		T7	292
all_pins[2]	100600291	1			T1	160793		T3	223821		T7	292

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	249994647	1			T1	404876		T3	570817		T7	754
values[0x1]	51806226	1			T1	77503		T3	100646		T7	122
transitions[0x0=>0x1]	51381305	1			T1	73588		T3	100476		T7	110
transitions[0x1=>0x0]	51381332	1			T1	73588		T3	100476		T7	110

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100093122	1			T1	160299		T3	223607		T7	280
all_pins[0]	values[0x1]	507169	1			T1	494		T3	214		T7	12
all_pins[0]	transitions[0x0=>0x1]	214296	1			T1	42		T3	44		T28	52
all_pins[0]	transitions[0x1=>0x0]	50677535	1			T1	69119		T3	100262		T7	98
all_pins[1]	values[0x0]	49629883	1			T1	91222		T3	123389		T7	182
all_pins[1]	values[0x1]	50970408	1			T1	69571		T3	100432		T7	110
all_pins[1]	transitions[0x0=>0x1]	50840351	1			T1	66152		T3	100432		T7	110
all_pins[1]	transitions[0x1=>0x0]	198592	1			T1	4019		T37	891		T38	5051
all_pins[2]	values[0x0]	100271642	1			T1	153355		T3	223821		T7	292
all_pins[2]	values[0x1]	328649	1			T1	7438		T37	1595		T38	8926
all_pins[2]	transitions[0x0=>0x1]	326658	1			T1	7394		T37	1581		T38	8872
all_pins[2]	transitions[0x1=>0x0]	505205	1			T1	450		T3	214		T7	12