Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	97544958	1			T1	292		T2	139		T3	135786
all_values[1]	97544958	1			T1	292		T2	139		T3	135786
all_values[2]	97544958	1			T1	292		T2	139		T3	135786

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

535646

1

T1

13

T2

3

T3

14053

auto[1]

292099228

1

T1

863

T2

414

T3

393305

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

291151674

1

T1

840

T2

417

T3

405714

auto[1]

1483200

1

T1

36

T3

1644

T7

48

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	185740	1			T3	101		T7	9		T22	6
all_values[0]	auto[0]	auto[1]	2024	1			T3	16		T7	4		T22	2
all_values[0]	auto[1]	auto[0]	96864818	1			T1	280		T2	139		T3	135137
all_values[0]	auto[1]	auto[1]	492376	1			T1	12		T3	532		T7	12
all_values[1]	auto[0]	auto[0]	182001	1			T2	1		T3	5074		T7	5
all_values[1]	auto[0]	auto[1]	1529	1			T3	11		T7	2		T22	2
all_values[1]	auto[1]	auto[0]	96868557	1			T1	280		T2	138		T3	130164
all_values[1]	auto[1]	auto[1]	492871	1			T1	12		T3	537		T7	14
all_values[2]	auto[0]	auto[0]	162970	1			T1	10		T2	2		T3	8836
all_values[2]	auto[0]	auto[1]	1382	1			T1	3		T3	15		T26	3
all_values[2]	auto[1]	auto[0]	96887588	1			T1	270		T2	137		T3	126402
all_values[2]	auto[1]	auto[1]	493018	1			T1	9		T3	533		T7	16