Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
377944 |
1 |
|
|
T1 |
18 |
|
T2 |
276 |
|
T3 |
400 |
auto[1] |
295392 |
1 |
|
|
T3 |
426 |
|
T7 |
16 |
|
T8 |
114 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
169069 |
1 |
|
|
T1 |
8 |
|
T2 |
66 |
|
T3 |
200 |
lower_val |
166357 |
1 |
|
|
T1 |
2 |
|
T2 |
61 |
|
T3 |
180 |
zero_val |
1820 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
10 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
261572 |
1 |
|
|
T1 |
6 |
|
T2 |
128 |
|
T3 |
318 |
lower_val |
263696 |
1 |
|
|
T1 |
12 |
|
T2 |
148 |
|
T3 |
300 |
zero_val |
148068 |
1 |
|
|
T3 |
208 |
|
T7 |
4 |
|
T8 |
54 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
47201 |
1 |
|
|
T1 |
2 |
|
T2 |
28 |
|
T3 |
57 |
higher_val |
higher_val |
auto[1] |
18542 |
1 |
|
|
T3 |
23 |
|
T8 |
7 |
|
T26 |
1 |
higher_val |
lower_val |
auto[0] |
47557 |
1 |
|
|
T1 |
6 |
|
T2 |
38 |
|
T3 |
42 |
higher_val |
lower_val |
auto[1] |
18542 |
1 |
|
|
T3 |
19 |
|
T7 |
1 |
|
T8 |
8 |
higher_val |
zero_val |
auto[0] |
93 |
1 |
|
|
T8 |
1 |
|
T9 |
1 |
|
T26 |
1 |
higher_val |
zero_val |
auto[1] |
37134 |
1 |
|
|
T3 |
59 |
|
T7 |
1 |
|
T8 |
18 |
lower_val |
higher_val |
auto[0] |
46425 |
1 |
|
|
T1 |
1 |
|
T2 |
29 |
|
T3 |
41 |
lower_val |
higher_val |
auto[1] |
18242 |
1 |
|
|
T3 |
26 |
|
T8 |
7 |
|
T9 |
2 |
lower_val |
lower_val |
auto[0] |
46721 |
1 |
|
|
T1 |
1 |
|
T2 |
32 |
|
T3 |
42 |
lower_val |
lower_val |
auto[1] |
18188 |
1 |
|
|
T3 |
25 |
|
T8 |
8 |
|
T9 |
2 |
lower_val |
zero_val |
auto[0] |
76 |
1 |
|
|
T13 |
1 |
|
T189 |
1 |
|
T190 |
1 |
lower_val |
zero_val |
auto[1] |
36705 |
1 |
|
|
T3 |
46 |
|
T8 |
9 |
|
T9 |
2 |
zero_val |
higher_val |
auto[0] |
522 |
1 |
|
|
T2 |
1 |
|
T7 |
1 |
|
T27 |
3 |
zero_val |
higher_val |
auto[1] |
140 |
1 |
|
|
T3 |
2 |
|
T13 |
2 |
|
T191 |
4 |
zero_val |
lower_val |
auto[0] |
580 |
1 |
|
|
T1 |
1 |
|
T3 |
3 |
|
T22 |
1 |
zero_val |
lower_val |
auto[1] |
143 |
1 |
|
|
T3 |
4 |
|
T192 |
1 |
|
T13 |
1 |
zero_val |
zero_val |
auto[0] |
257 |
1 |
|
|
T3 |
1 |
|
T8 |
1 |
|
T9 |
1 |
zero_val |
zero_val |
auto[1] |
178 |
1 |
|
|
T27 |
1 |
|
T57 |
2 |
|
T192 |
3 |