Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	97544958	1			T1	292		T2	139		T3	135786
all_pins[1]	97544958	1			T1	292		T2	139		T3	135786
all_pins[2]	97544958	1			T1	292		T2	139		T3	135786

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	242582387	1			T1	751		T2	353		T3	334203
values[0x1]	50052487	1			T1	125		T2	64		T3	73155
transitions[0x0=>0x1]	49625588	1			T1	113		T2	64		T3	66437
transitions[0x1=>0x0]	49625610	1			T1	113		T2	64		T3	66437

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	97052582	1			T1	280		T2	139		T3	135254
all_pins[0]	values[0x1]	492376	1			T1	12		T3	532		T7	12
all_pins[0]	transitions[0x0=>0x1]	207526	1			T3	54		T22	32		T8	4
all_pins[0]	transitions[0x1=>0x0]	48925117	1			T1	101		T2	64		T3	58472
all_pins[1]	values[0x0]	48334991	1			T1	179		T2	75		T3	76836
all_pins[1]	values[0x1]	49209967	1			T1	113		T2	64		T3	58950
all_pins[1]	transitions[0x0=>0x1]	49070089	1			T1	113		T2	64		T3	52798
all_pins[1]	transitions[0x1=>0x0]	210266	1			T3	7521		T13	2475		T78	765
all_pins[2]	values[0x0]	97194814	1			T1	292		T2	139		T3	122113
all_pins[2]	values[0x1]	350144	1			T3	13673		T13	4004		T78	766
all_pins[2]	transitions[0x0=>0x1]	347973	1			T3	13585		T13	3981		T78	766
all_pins[2]	transitions[0x1=>0x0]	490227	1			T1	12		T3	444		T7	12