Summary for Variable in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for in_app_keymgr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
330869 |
1 |
|
|
T1 |
9 |
|
T2 |
202 |
|
T3 |
435 |
auto[1] |
3452 |
1 |
|
|
T2 |
74 |
|
T3 |
23 |
|
T8 |
11 |
Summary for Variable kmac_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
296400 |
1 |
|
|
T2 |
128 |
|
T3 |
159 |
|
T22 |
42 |
auto[1] |
37921 |
1 |
|
|
T1 |
9 |
|
T2 |
148 |
|
T3 |
299 |
Summary for Variable sideload
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sideload
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
320236 |
1 |
|
|
T1 |
9 |
|
T2 |
182 |
|
T3 |
355 |
auto[1] |
14085 |
1 |
|
|
T2 |
94 |
|
T3 |
103 |
|
T8 |
24 |
Summary for Cross sideload_cross
Samples crossed: sideload kmac_mode in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins for sideload_cross
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sw_kmac_valid_sideload |
14085 |
1 |
|
|
T2 |
94 |
|
T3 |
103 |
|
T8 |
24 |
sw_kmac_invalid_sideload |
320236 |
1 |
|
|
T1 |
9 |
|
T2 |
182 |
|
T3 |
355 |
app_valid_sideload |
14085 |
1 |
|
|
T2 |
94 |
|
T3 |
103 |
|
T8 |
24 |
app_invalid_sideload |
320236 |
1 |
|
|
T1 |
9 |
|
T2 |
182 |
|
T3 |
355 |