Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10619711 |
1 |
|
|
T1 |
96 |
|
T2 |
4058 |
|
T3 |
52574 |
auto[1] |
10619670 |
1 |
|
|
T1 |
96 |
|
T2 |
4058 |
|
T3 |
52574 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21007717 |
1 |
|
|
T1 |
192 |
|
T2 |
8116 |
|
T3 |
104616 |
triple_byte_access |
77244 |
1 |
|
|
T3 |
148 |
|
T22 |
52 |
|
T8 |
16 |
halfword_access |
77496 |
1 |
|
|
T3 |
182 |
|
T22 |
56 |
|
T8 |
18 |
byte_access |
76924 |
1 |
|
|
T3 |
202 |
|
T22 |
70 |
|
T8 |
18 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10503879 |
1 |
|
|
T1 |
96 |
|
T2 |
4058 |
|
T3 |
52308 |
auto[0] |
triple_byte_access |
38622 |
1 |
|
|
T3 |
74 |
|
T22 |
26 |
|
T8 |
8 |
auto[0] |
halfword_access |
38748 |
1 |
|
|
T3 |
91 |
|
T22 |
28 |
|
T8 |
9 |
auto[0] |
byte_access |
38462 |
1 |
|
|
T3 |
101 |
|
T22 |
35 |
|
T8 |
9 |
auto[1] |
word_access |
10503838 |
1 |
|
|
T1 |
96 |
|
T2 |
4058 |
|
T3 |
52308 |
auto[1] |
triple_byte_access |
38622 |
1 |
|
|
T3 |
74 |
|
T22 |
26 |
|
T8 |
8 |
auto[1] |
halfword_access |
38748 |
1 |
|
|
T3 |
91 |
|
T22 |
28 |
|
T8 |
9 |
auto[1] |
byte_access |
38462 |
1 |
|
|
T3 |
101 |
|
T22 |
35 |
|
T8 |
9 |