Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
266 |
1 |
|
|
T125 |
7 |
|
T127 |
7 |
|
T173 |
7 |
all_values[1] |
266 |
1 |
|
|
T125 |
7 |
|
T127 |
7 |
|
T173 |
7 |
all_values[2] |
266 |
1 |
|
|
T125 |
7 |
|
T127 |
7 |
|
T173 |
7 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
444 |
1 |
|
|
T125 |
11 |
|
T127 |
13 |
|
T173 |
7 |
auto[1] |
354 |
1 |
|
|
T125 |
10 |
|
T127 |
8 |
|
T173 |
14 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
318 |
1 |
|
|
T125 |
7 |
|
T127 |
11 |
|
T173 |
3 |
auto[1] |
480 |
1 |
|
|
T125 |
14 |
|
T127 |
10 |
|
T173 |
18 |
Summary for Variable cp_intr_test
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_test
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
465 |
1 |
|
|
T125 |
10 |
|
T127 |
14 |
|
T173 |
11 |
auto[1] |
333 |
1 |
|
|
T125 |
11 |
|
T127 |
7 |
|
T173 |
10 |
Summary for Cross intr_test_cg_cc
Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for intr_test_cg_cc
Bins
cp_intr | cp_intr_test | cp_intr_en | cp_intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
auto[0] |
71 |
1 |
|
|
T125 |
3 |
|
T127 |
2 |
|
T173 |
1 |
all_values[0] |
auto[0] |
auto[0] |
auto[1] |
20 |
1 |
|
|
T127 |
1 |
|
T169 |
1 |
|
T174 |
1 |
all_values[0] |
auto[0] |
auto[1] |
auto[0] |
40 |
1 |
|
|
T127 |
2 |
|
T173 |
1 |
|
T169 |
1 |
all_values[0] |
auto[0] |
auto[1] |
auto[1] |
23 |
1 |
|
|
T125 |
1 |
|
T173 |
2 |
|
T175 |
2 |
all_values[0] |
auto[1] |
auto[0] |
auto[1] |
70 |
1 |
|
|
T125 |
1 |
|
T127 |
2 |
|
T173 |
2 |
all_values[0] |
auto[1] |
auto[1] |
auto[1] |
42 |
1 |
|
|
T125 |
2 |
|
T173 |
1 |
|
T168 |
1 |
all_values[1] |
auto[0] |
auto[0] |
auto[0] |
57 |
1 |
|
|
T125 |
1 |
|
T127 |
3 |
|
T168 |
1 |
all_values[1] |
auto[0] |
auto[0] |
auto[1] |
28 |
1 |
|
|
T127 |
1 |
|
T176 |
3 |
|
T174 |
1 |
all_values[1] |
auto[0] |
auto[1] |
auto[0] |
45 |
1 |
|
|
T125 |
2 |
|
T127 |
2 |
|
T174 |
1 |
all_values[1] |
auto[0] |
auto[1] |
auto[1] |
27 |
1 |
|
|
T125 |
1 |
|
T173 |
2 |
|
T169 |
2 |
all_values[1] |
auto[1] |
auto[0] |
auto[1] |
60 |
1 |
|
|
T125 |
2 |
|
T127 |
1 |
|
T173 |
2 |
all_values[1] |
auto[1] |
auto[1] |
auto[1] |
49 |
1 |
|
|
T125 |
1 |
|
T173 |
3 |
|
T168 |
1 |
all_values[2] |
auto[0] |
auto[0] |
auto[0] |
54 |
1 |
|
|
T173 |
1 |
|
T168 |
1 |
|
T169 |
1 |
all_values[2] |
auto[0] |
auto[0] |
auto[1] |
21 |
1 |
|
|
T125 |
1 |
|
T168 |
1 |
|
T176 |
1 |
all_values[2] |
auto[0] |
auto[1] |
auto[0] |
51 |
1 |
|
|
T125 |
1 |
|
T127 |
2 |
|
T169 |
2 |
all_values[2] |
auto[0] |
auto[1] |
auto[1] |
28 |
1 |
|
|
T127 |
1 |
|
T173 |
4 |
|
T169 |
1 |
all_values[2] |
auto[1] |
auto[0] |
auto[1] |
63 |
1 |
|
|
T125 |
3 |
|
T127 |
3 |
|
T173 |
1 |
all_values[2] |
auto[1] |
auto[1] |
auto[1] |
49 |
1 |
|
|
T125 |
2 |
|
T127 |
1 |
|
T173 |
1 |
User Defined Cross Bins for intr_test_cg_cc
Excluded/Illegal bins
NAME | COUNT | STATUS |
test_1_state_0 |
0 |
Illegal |