Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	97061670	1			T2	217807		T7	5950		T8	463707
all_values[1]	97061670	1			T2	217807		T7	5950		T8	463707
all_values[2]	97061670	1			T2	217807		T7	5950		T8	463707

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

534746

1

T2

3

T7

903

T8

7

auto[1]

290650264

1

T2

653418

T7

16947

T8

139111

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

289713744

1

T2

651672

T7

17709

T8

138091

auto[1]

1471266

1

T2

1749

T7

141

T8

10209

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	187225	1			T7	299		T8	3		T17	4
all_values[0]	auto[0]	auto[1]	1819	1			T7	2		T8	4		T17	2
all_values[0]	auto[1]	auto[0]	96384023	1			T2	217224		T7	5604		T8	460301
all_values[0]	auto[1]	auto[1]	488603	1			T2	583		T7	45		T8	3399
all_values[1]	auto[0]	auto[0]	175022	1			T2	2		T7	299		T10	3
all_values[1]	auto[0]	auto[1]	1472	1			T2	1		T7	2		T10	2
all_values[1]	auto[1]	auto[0]	96396226	1			T2	217222		T7	5604		T8	460304
all_values[1]	auto[1]	auto[1]	488950	1			T2	582		T7	45		T8	3403
all_values[2]	auto[0]	auto[0]	167731	1			T7	299		T14	23		T17	10
all_values[2]	auto[0]	auto[1]	1477	1			T7	2		T14	9		T17	3
all_values[2]	auto[1]	auto[0]	96403517	1			T2	217224		T7	5604		T8	460304
all_values[2]	auto[1]	auto[1]	488945	1			T2	583		T7	45		T8	3403