Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
319198 |
1 |
|
|
T2 |
2 |
|
T7 |
70 |
|
T8 |
2 |
auto[1] |
348258 |
1 |
|
|
T2 |
778 |
|
T8 |
4528 |
|
T14 |
4528 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
167525 |
1 |
|
|
T2 |
196 |
|
T7 |
29 |
|
T8 |
1160 |
lower_val |
165091 |
1 |
|
|
T2 |
172 |
|
T7 |
12 |
|
T8 |
1108 |
zero_val |
1789 |
1 |
|
|
T2 |
1 |
|
T7 |
1 |
|
T8 |
7 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
247170 |
1 |
|
|
T2 |
196 |
|
T7 |
30 |
|
T8 |
1166 |
lower_val |
246330 |
1 |
|
|
T2 |
202 |
|
T7 |
40 |
|
T8 |
1122 |
zero_val |
173956 |
1 |
|
|
T2 |
382 |
|
T8 |
2242 |
|
T14 |
2308 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
39951 |
1 |
|
|
T7 |
13 |
|
T15 |
91 |
|
T17 |
6 |
higher_val |
higher_val |
auto[1] |
22138 |
1 |
|
|
T2 |
43 |
|
T8 |
291 |
|
T14 |
287 |
higher_val |
lower_val |
auto[0] |
39067 |
1 |
|
|
T7 |
16 |
|
T15 |
83 |
|
T17 |
4 |
higher_val |
lower_val |
auto[1] |
22332 |
1 |
|
|
T2 |
50 |
|
T8 |
299 |
|
T14 |
291 |
higher_val |
zero_val |
auto[0] |
80 |
1 |
|
|
T189 |
1 |
|
T190 |
1 |
|
T191 |
1 |
higher_val |
zero_val |
auto[1] |
43957 |
1 |
|
|
T2 |
103 |
|
T8 |
570 |
|
T14 |
616 |
lower_val |
higher_val |
auto[0] |
39450 |
1 |
|
|
T7 |
5 |
|
T15 |
55 |
|
T17 |
1 |
lower_val |
higher_val |
auto[1] |
21445 |
1 |
|
|
T2 |
38 |
|
T8 |
280 |
|
T14 |
267 |
lower_val |
lower_val |
auto[0] |
39459 |
1 |
|
|
T7 |
7 |
|
T15 |
79 |
|
T17 |
1 |
lower_val |
lower_val |
auto[1] |
21625 |
1 |
|
|
T2 |
43 |
|
T8 |
268 |
|
T14 |
290 |
lower_val |
zero_val |
auto[0] |
91 |
1 |
|
|
T8 |
1 |
|
T43 |
1 |
|
T31 |
1 |
lower_val |
zero_val |
auto[1] |
43021 |
1 |
|
|
T2 |
91 |
|
T8 |
559 |
|
T14 |
576 |
zero_val |
higher_val |
auto[0] |
516 |
1 |
|
|
T7 |
1 |
|
T15 |
1 |
|
T17 |
1 |
zero_val |
higher_val |
auto[1] |
125 |
1 |
|
|
T8 |
1 |
|
T42 |
2 |
|
T189 |
2 |
zero_val |
lower_val |
auto[0] |
552 |
1 |
|
|
T2 |
1 |
|
T14 |
1 |
|
T22 |
1 |
zero_val |
lower_val |
auto[1] |
134 |
1 |
|
|
T8 |
1 |
|
T31 |
2 |
|
T190 |
1 |
zero_val |
zero_val |
auto[0] |
225 |
1 |
|
|
T8 |
1 |
|
T43 |
1 |
|
T189 |
1 |
zero_val |
zero_val |
auto[1] |
237 |
1 |
|
|
T8 |
4 |
|
T42 |
6 |
|
T189 |
4 |