Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

Group : kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

---

Summary for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hash_mode	3	0	3	100.00	100	1	1	0
kmac_mode	2	0	2	100.00	100	1	1	2
msgfifo_depth	11	0	11	100.00	100	1	1	0
msgfifo_empty	2	0	2	100.00	100	1	1	2
msgfifo_full	2	0	2	100.00	100	1	1	2

Summary for Variable hash_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for hash_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
cshake	14820949	1			T7	9256		T17	244		T10	76621
shake	54828606	1			T7	2999		T8	487726		T14	478550
sha3	34281111	1			T2	217026		T7	408		T15	161652

---

Summary for Variable kmac_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_mode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

89108643

1

T2

217026

T7

3407

T8

487726

auto[1]

14822023

1

T7

9256

T17

244

T10

76621

---

Summary for Variable msgfifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for msgfifo_depth

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
depth[0x00]	89380627	1			T2	216515		T7	10470		T8	374698
depth[0x01]	3448765	1			T2	511		T7	305		T8	25421
depth[0x02]	2910169	1			T7	331		T8	27911		T14	27037
depth[0x03]	2715800	1			T7	309		T8	26138		T14	25310
depth[0x04]	2441111	1			T7	284		T8	22981		T14	24285
depth[0x05]	1362977	1			T7	196		T8	10576		T14	12208
depth[0x06]	339173	1			T7	60		T8	1		T14	4
depth[0x07]	270211	1			T7	54		T10	7950		T11	259
depth[0x08]	267098	1			T7	64		T10	7946		T11	315
depth[0x09]	252218	1			T7	55		T10	7768		T11	251
depth[0x0a]	542517	1			T7	535		T10	11995		T11	2252

---

Summary for Variable msgfifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msgfifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14550039

1

T2

511

T7

2193

T8

113028

auto[1]

89380627

1

T2

216515

T7

10470

T8

374698

---

Summary for Variable msgfifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msgfifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

103388149

1

T2

217026

T7

12128

T8

487726

auto[1]

542517

1

T7

535

T10

11995

T11

2252