Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	97061670	1			T2	217807		T7	5950		T8	463707
all_pins[1]	97061670	1			T2	217807		T7	5950		T8	463707
all_pins[2]	97061670	1			T2	217807		T7	5950		T8	463707

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	290360760	1			T2	652838		T7	17340		T8	138772
values[0x1]	824250	1			T2	583		T7	510		T8	3399
transitions[0x0=>0x1]	821892	1			T2	583		T7	510		T8	3399
transitions[0x1=>0x0]	821921	1			T2	583		T7	510		T8	3399

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	96573067	1			T2	217224		T7	5905		T8	460308
all_pins[0]	values[0x1]	488603	1			T2	583		T7	45		T8	3399
all_pins[0]	transitions[0x0=>0x1]	488592	1			T2	583		T7	45		T8	3399
all_pins[0]	transitions[0x1=>0x0]	5238	1			T7	11		T10	5		T11	77
all_pins[1]	values[0x0]	97056421	1			T2	217807		T7	5939		T8	463707
all_pins[1]	values[0x1]	5249	1			T7	11		T10	5		T11	77
all_pins[1]	transitions[0x0=>0x1]	4970	1			T7	11		T10	5		T11	77
all_pins[1]	transitions[0x1=>0x0]	330119	1			T7	454		T24	849		T12	119
all_pins[2]	values[0x0]	96731272	1			T2	217807		T7	5496		T8	463707
all_pins[2]	values[0x1]	330398	1			T7	454		T24	849		T12	119
all_pins[2]	transitions[0x0=>0x1]	328330	1			T7	454		T24	848		T12	119
all_pins[2]	transitions[0x1=>0x0]	486564	1			T2	583		T7	45		T8	3399