Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	619	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5303	1			T7	7		T10	13		T22	21
len_601_800	11847	1			T7	6		T10	17		T22	42
len_401_600	7928	1			T7	11		T10	20		T22	17
len_201_400	15737	1			T7	1		T8	251		T14	251
len_65_200	71144	1			T7	2		T8	680		T14	680
len_min_for_xof_require_squeeze	968	1			T8	10		T14	10		T42	10
len_keccak_block_sizes[72]	716	1			T8	5		T14	5		T42	5
len_keccak_block_sizes[104]	734	1			T8	5		T14	5		T42	5
len_keccak_block_sizes[136]	718	1			T8	5		T14	5		T42	5
len_keccak_block_sizes[144]	285	1			T8	5		T14	5		T42	5
len_keccak_block_sizes[168]	278	1			T8	5		T14	5		T42	5
len_datapath_width	13476	1			T8	5		T14	5		T17	3
len_2_63	206275	1			T2	390		T7	1		T8	1329
len_1	50	1			T22	1		T31	2		T192	1