Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	97368657	1			T1	17092		T2	300		T3	458905
all_values[1]	97368657	1			T1	17092		T2	300		T3	458905
all_values[2]	97368657	1			T1	17092		T2	300		T3	458905

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

517706

1

T2

20

T3

6

T7

13

auto[1]

291588265

1

T1

51276

T2

880

T3

137670

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

290629440

1

T1

50757

T2

861

T3

136660

auto[1]

1476531

1

T1

519

T2

39

T3

10110

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	189930	1			T3	1		T7	1		T8	214
all_values[0]	auto[0]	auto[1]	2010	1			T3	2		T7	2		T8	2
all_values[0]	auto[1]	auto[0]	96686550	1			T1	16919		T2	287		T3	455534
all_values[0]	auto[1]	auto[1]	490167	1			T1	173		T2	13		T3	3368
all_values[1]	auto[0]	auto[0]	135072	1			T2	11		T7	4		T14	33
all_values[1]	auto[0]	auto[1]	1515	1			T2	2		T7	3		T14	2
all_values[1]	auto[1]	auto[0]	96741408	1			T1	16919		T2	276		T3	455535
all_values[1]	auto[1]	auto[1]	490662	1			T1	173		T2	11		T3	3370
all_values[2]	auto[0]	auto[0]	187474	1			T2	6		T3	1		T7	1
all_values[2]	auto[0]	auto[1]	1705	1			T2	1		T3	2		T7	2
all_values[2]	auto[1]	auto[0]	96689006	1			T1	16919		T2	281		T3	455534
all_values[2]	auto[1]	auto[1]	490472	1			T1	173		T2	12		T3	3368