Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	9976	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	8794	1			T3	38		T7	19		T10	31
len_5001_7500	14101	1			T3	36		T7	18		T10	93
len_2501_5000	8947	1			T3	36		T7	18		T10	22
len_1025_2500	5257	1			T3	22		T7	11		T10	10
len_769_1024	6167	1			T1	23		T3	4		T7	2
len_513_768	6861	1			T1	32		T3	4		T7	2
len_257_512	20869	1			T1	33		T3	52		T7	2
len_0_256	246963	1			T1	30		T2	9		T3	2017
len_keccak_block_sizes[72]	693	1			T3	3		T7	2		T9	1
len_keccak_block_sizes[104]	599	1			T3	3		T7	2		T52	2
len_keccak_block_sizes[136]	504	1			T3	3		T7	2		T52	2
len_keccak_block_sizes[144]	411	1			T3	3		T173	3		T86	3
len_keccak_block_sizes[168]	311	1			T3	3		T8	1		T173	3
len_1	734	1			T3	3		T7	2		T52	2
len_0	1185	1			T3	3		T7	2		T10	4