Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	97368657	1			T1	17092		T2	300		T3	458905
all_pins[1]	97368657	1			T1	17092		T2	300		T3	458905
all_pins[2]	97368657	1			T1	17092		T2	300		T3	458905

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	291285465	1			T1	51103		T2	887		T3	137334
values[0x1]	820506	1			T1	173		T2	13		T3	3368
transitions[0x0=>0x1]	818283	1			T1	173		T2	13		T3	3368
transitions[0x1=>0x0]	818314	1			T1	173		T2	13		T3	3368

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	96878490	1			T1	16919		T2	287		T3	455537
all_pins[0]	values[0x1]	490167	1			T1	173		T2	13		T3	3368
all_pins[0]	transitions[0x0=>0x1]	490164	1			T1	173		T2	13		T3	3368
all_pins[0]	transitions[0x1=>0x0]	6517	1			T9	6		T10	67		T11	39
all_pins[1]	values[0x0]	97362137	1			T1	17092		T2	300		T3	458905
all_pins[1]	values[0x1]	6520	1			T9	6		T10	67		T11	39
all_pins[1]	transitions[0x0=>0x1]	6244	1			T9	6		T10	67		T11	39
all_pins[1]	transitions[0x1=>0x0]	323543	1			T15	2350		T16	4192		T17	1625
all_pins[2]	values[0x0]	97044838	1			T1	17092		T2	300		T3	458905
all_pins[2]	values[0x1]	323819	1			T15	2350		T16	4199		T17	1625
all_pins[2]	transitions[0x0=>0x1]	321875	1			T15	2350		T16	4162		T17	1625
all_pins[2]	transitions[0x1=>0x0]	488254	1			T1	173		T2	13		T3	3368