Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	686	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5616	1			T1	16		T8	13		T14	35
len_601_800	12612	1			T1	43		T8	49		T14	46
len_401_600	8419	1			T1	34		T8	28		T14	47
len_201_400	15284	1			T1	12		T3	251		T8	16
len_65_200	70537	1			T1	6		T3	680		T8	2
len_min_for_xof_require_squeeze	962	1			T1	1		T3	10		T8	1
len_keccak_block_sizes[72]	732	1			T3	5		T173	5		T16	2
len_keccak_block_sizes[104]	724	1			T3	5		T12	1		T40	2
len_keccak_block_sizes[136]	731	1			T3	5		T40	1		T173	5
len_keccak_block_sizes[144]	265	1			T3	5		T40	1		T173	5
len_keccak_block_sizes[168]	252	1			T3	5		T14	1		T12	1
len_datapath_width	13449	1			T2	3		T3	5		T14	1
len_2_63	206452	1			T1	53		T2	6		T3	1329
len_1	62	1			T55	2		T16	1		T174	1