Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10559709 |
1 |
|
|
T1 |
20668 |
|
T2 |
96 |
|
T3 |
47900 |
auto[1] |
10559705 |
1 |
|
|
T1 |
20668 |
|
T2 |
96 |
|
T3 |
47900 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
20889478 |
1 |
|
|
T1 |
41158 |
|
T2 |
192 |
|
T3 |
93928 |
triple_byte_access |
76364 |
1 |
|
|
T1 |
60 |
|
T3 |
620 |
|
T8 |
40 |
halfword_access |
77054 |
1 |
|
|
T1 |
62 |
|
T3 |
632 |
|
T8 |
62 |
byte_access |
76518 |
1 |
|
|
T1 |
56 |
|
T3 |
620 |
|
T8 |
58 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10444741 |
1 |
|
|
T1 |
20579 |
|
T2 |
96 |
|
T3 |
46964 |
auto[0] |
triple_byte_access |
38182 |
1 |
|
|
T1 |
30 |
|
T3 |
310 |
|
T8 |
20 |
auto[0] |
halfword_access |
38527 |
1 |
|
|
T1 |
31 |
|
T3 |
316 |
|
T8 |
31 |
auto[0] |
byte_access |
38259 |
1 |
|
|
T1 |
28 |
|
T3 |
310 |
|
T8 |
29 |
auto[1] |
word_access |
10444737 |
1 |
|
|
T1 |
20579 |
|
T2 |
96 |
|
T3 |
46964 |
auto[1] |
triple_byte_access |
38182 |
1 |
|
|
T1 |
30 |
|
T3 |
310 |
|
T8 |
20 |
auto[1] |
halfword_access |
38527 |
1 |
|
|
T1 |
31 |
|
T3 |
316 |
|
T8 |
31 |
auto[1] |
byte_access |
38259 |
1 |
|
|
T1 |
28 |
|
T3 |
310 |
|
T8 |
29 |