Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	98831854	1			T1	221302		T2	6252		T3	27825
all_values[1]	98831854	1			T1	221302		T2	6252		T3	27825
all_values[2]	98831854	1			T1	221302		T2	6252		T3	27825

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

557361

1

T1

26

T2

30

T3

457

auto[1]

295938201

1

T1

663880

T2

18726

T3

83018

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

294981732

1

T1

662157

T2

18576

T3

82593

auto[1]

1513830

1

T1

1749

T2

180

T3

882

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	159465	1			T1	1		T2	28		T3	194
all_values[0]	auto[0]	auto[1]	2183	1			T1	2		T2	2		T3	4
all_values[0]	auto[1]	auto[0]	98167779	1			T1	220718		T2	6164		T3	27337
all_values[0]	auto[1]	auto[1]	502427	1			T1	581		T2	58		T3	290
all_values[1]	auto[0]	auto[0]	213830	1			T1	4		T14	6		T15	9
all_values[1]	auto[0]	auto[1]	1629	1			T1	3		T14	5		T15	3
all_values[1]	auto[1]	auto[0]	98113414	1			T1	220715		T2	6192		T3	27531
all_values[1]	auto[1]	auto[1]	502981	1			T1	580		T2	60		T3	294
all_values[2]	auto[0]	auto[0]	178527	1			T1	11		T3	254		T11	14
all_values[2]	auto[0]	auto[1]	1727	1			T1	5		T3	5		T11	9
all_values[2]	auto[1]	auto[0]	98148717	1			T1	220708		T2	6192		T3	27277
all_values[2]	auto[1]	auto[1]	502883	1			T1	578		T2	60		T3	289