Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
366342 |
1 |
|
|
T1 |
780 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
321084 |
1 |
|
|
T2 |
80 |
|
T3 |
390 |
|
T11 |
778 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
172376 |
1 |
|
|
T1 |
190 |
|
T2 |
26 |
|
T3 |
120 |
lower_val |
170819 |
1 |
|
|
T1 |
176 |
|
T2 |
26 |
|
T3 |
98 |
zero_val |
1902 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
262778 |
1 |
|
|
T1 |
380 |
|
T2 |
16 |
|
T3 |
86 |
lower_val |
263376 |
1 |
|
|
T1 |
400 |
|
T2 |
32 |
|
T3 |
104 |
zero_val |
161272 |
1 |
|
|
T2 |
34 |
|
T3 |
202 |
|
T11 |
384 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
45760 |
1 |
|
|
T1 |
99 |
|
T14 |
50 |
|
T15 |
60 |
higher_val |
higher_val |
auto[1] |
19992 |
1 |
|
|
T2 |
4 |
|
T3 |
24 |
|
T11 |
54 |
higher_val |
lower_val |
auto[0] |
46225 |
1 |
|
|
T1 |
91 |
|
T14 |
62 |
|
T15 |
56 |
higher_val |
lower_val |
auto[1] |
19932 |
1 |
|
|
T2 |
12 |
|
T3 |
33 |
|
T11 |
48 |
higher_val |
zero_val |
auto[0] |
99 |
1 |
|
|
T7 |
1 |
|
T33 |
1 |
|
T90 |
2 |
higher_val |
zero_val |
auto[1] |
40368 |
1 |
|
|
T2 |
10 |
|
T3 |
63 |
|
T11 |
108 |
lower_val |
higher_val |
auto[0] |
45211 |
1 |
|
|
T1 |
93 |
|
T12 |
1 |
|
T14 |
55 |
lower_val |
higher_val |
auto[1] |
20221 |
1 |
|
|
T2 |
5 |
|
T3 |
20 |
|
T11 |
42 |
lower_val |
lower_val |
auto[0] |
45685 |
1 |
|
|
T1 |
83 |
|
T14 |
51 |
|
T15 |
47 |
lower_val |
lower_val |
auto[1] |
19878 |
1 |
|
|
T2 |
10 |
|
T3 |
22 |
|
T11 |
51 |
lower_val |
zero_val |
auto[0] |
80 |
1 |
|
|
T2 |
1 |
|
T19 |
1 |
|
T104 |
1 |
lower_val |
zero_val |
auto[1] |
39744 |
1 |
|
|
T2 |
10 |
|
T3 |
56 |
|
T11 |
87 |
zero_val |
higher_val |
auto[0] |
554 |
1 |
|
|
T1 |
1 |
|
T11 |
1 |
|
T12 |
1 |
zero_val |
higher_val |
auto[1] |
149 |
1 |
|
|
T180 |
1 |
|
T181 |
1 |
|
T38 |
1 |
zero_val |
lower_val |
auto[0] |
562 |
1 |
|
|
T3 |
1 |
|
T14 |
1 |
|
T16 |
1 |
zero_val |
lower_val |
auto[1] |
156 |
1 |
|
|
T54 |
2 |
|
T90 |
3 |
|
T181 |
1 |
zero_val |
zero_val |
auto[0] |
276 |
1 |
|
|
T2 |
1 |
|
T7 |
1 |
|
T19 |
1 |
zero_val |
zero_val |
auto[1] |
205 |
1 |
|
|
T180 |
1 |
|
T38 |
1 |
|
T49 |
2 |