Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	98831854	1			T1	221302		T2	6252		T3	27825
all_pins[1]	98831854	1			T1	221302		T2	6252		T3	27825
all_pins[2]	98831854	1			T1	221302		T2	6252		T3	27825

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	295649988	1			T1	663325		T2	18625		T3	83068
values[0x1]	845574	1			T1	581		T2	131		T3	407
transitions[0x0=>0x1]	843199	1			T1	581		T2	131		T3	407
transitions[0x1=>0x0]	843217	1			T1	581		T2	131		T3	407

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98329427	1			T1	220721		T2	6194		T3	27535
all_pins[0]	values[0x1]	502427	1			T1	581		T2	58		T3	290
all_pins[0]	transitions[0x0=>0x1]	502413	1			T1	581		T2	58		T3	290
all_pins[0]	transitions[0x1=>0x0]	6146	1			T3	117		T8	67		T20	48
all_pins[1]	values[0x0]	98825694	1			T1	221302		T2	6252		T3	27708
all_pins[1]	values[0x1]	6160	1			T3	117		T8	67		T20	48
all_pins[1]	transitions[0x0=>0x1]	5819	1			T3	117		T8	67		T20	48
all_pins[1]	transitions[0x1=>0x0]	336646	1			T2	73		T8	428		T54	1479
all_pins[2]	values[0x0]	98494867	1			T1	221302		T2	6179		T3	27825
all_pins[2]	values[0x1]	336987	1			T2	73		T8	428		T54	1479
all_pins[2]	transitions[0x0=>0x1]	334967	1			T2	73		T8	428		T54	1478
all_pins[2]	transitions[0x1=>0x0]	500425	1			T1	581		T2	58		T3	290