Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.59 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 2 16 88.89


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 2 16 88.89 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 272 1 T128 4 T129 7 T158 7
all_values[1] 272 1 T128 4 T129 7 T158 7
all_values[2] 272 1 T128 4 T129 7 T158 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 473 1 T128 7 T129 13 T158 11
auto[1] 343 1 T128 5 T129 8 T158 10


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 369 1 T128 9 T129 9 T158 10
auto[1] 447 1 T128 3 T129 12 T158 11


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 488 1 T128 10 T129 10 T158 14
auto[1] 328 1 T128 2 T129 11 T158 7


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 2 16 88.89 2
Automatically Generated Cross Bins 18 2 16 88.89 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[1]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 63 1 T128 4 T158 1 T159 2
all_values[0] auto[0] auto[0] auto[1] 35 1 T154 4 T160 1 T159 2
all_values[0] auto[0] auto[1] auto[0] 37 1 T129 4 T159 1 T161 1
all_values[0] auto[0] auto[1] auto[1] 23 1 T158 3 T154 1 T160 1
all_values[0] auto[1] auto[0] auto[1] 68 1 T129 2 T158 1 T154 2
all_values[0] auto[1] auto[1] auto[1] 46 1 T129 1 T158 2 T160 1
all_values[1] auto[0] auto[0] auto[0] 75 1 T129 4 T158 3 T154 1
all_values[1] auto[0] auto[1] auto[0] 86 1 T128 3 T158 3 T154 1
all_values[1] auto[1] auto[0] auto[1] 60 1 T128 1 T129 3 T154 3
all_values[1] auto[1] auto[1] auto[1] 51 1 T158 1 T154 2 T160 2
all_values[2] auto[0] auto[0] auto[0] 69 1 T128 1 T129 1 T158 3
all_values[2] auto[0] auto[0] auto[1] 35 1 T128 1 T158 1 T154 1
all_values[2] auto[0] auto[1] auto[0] 39 1 T128 1 T154 1 T159 1
all_values[2] auto[0] auto[1] auto[1] 26 1 T129 1 T160 2 T161 1
all_values[2] auto[1] auto[0] auto[1] 68 1 T129 3 T158 2 T154 2
all_values[2] auto[1] auto[1] auto[1] 35 1 T128 1 T129 2 T158 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%