Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99960985	1			T1	21326		T2	1436		T7	161397
all_values[1]	99960985	1			T1	21326		T2	1436		T7	161397
all_values[2]	99960985	1			T1	21326		T2	1436		T7	161397

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

527602

1

T1

255

T2

53

T7

3

auto[1]

299355353

1

T1

63723

T2

4255

T7

484188

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

298364193

1

T1

63390

T2

3687

T7

482799

auto[1]

1518762

1

T1

588

T2

621

T7

1392

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	169016	1			T2	4		T7	1		T12	1
all_values[0]	auto[0]	auto[1]	2017	1			T2	2		T7	2		T12	2
all_values[0]	auto[1]	auto[0]	99285715	1			T1	21130		T2	1225		T7	160932
all_values[0]	auto[1]	auto[1]	504237	1			T1	196		T2	205		T7	462
all_values[1]	auto[0]	auto[0]	164276	1			T12	4		T8	77		T9	22
all_values[1]	auto[0]	auto[1]	1544	1			T12	3		T8	2		T9	1
all_values[1]	auto[1]	auto[0]	99290455	1			T1	21130		T2	1229		T7	160933
all_values[1]	auto[1]	auto[1]	504710	1			T1	196		T2	207		T7	464
all_values[2]	auto[0]	auto[0]	189151	1			T1	254		T2	38		T12	1
all_values[2]	auto[0]	auto[1]	1598	1			T1	1		T2	9		T12	2
all_values[2]	auto[1]	auto[0]	99265580	1			T1	20876		T2	1191		T7	160933
all_values[2]	auto[1]	auto[1]	504656	1			T1	195		T2	198		T7	464