Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349584 |
1 |
|
|
T1 |
288 |
|
T2 |
282 |
|
T7 |
2 |
auto[1] |
339660 |
1 |
|
|
T7 |
618 |
|
T12 |
746 |
|
T8 |
262 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173256 |
1 |
|
|
T1 |
66 |
|
T2 |
74 |
|
T7 |
156 |
lower_val |
171282 |
1 |
|
|
T1 |
54 |
|
T2 |
44 |
|
T7 |
181 |
zero_val |
1844 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
259304 |
1 |
|
|
T1 |
144 |
|
T2 |
134 |
|
T7 |
160 |
lower_val |
259006 |
1 |
|
|
T1 |
144 |
|
T2 |
148 |
|
T7 |
138 |
zero_val |
170934 |
1 |
|
|
T7 |
322 |
|
T12 |
382 |
|
T8 |
122 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
44318 |
1 |
|
|
T1 |
40 |
|
T2 |
27 |
|
T9 |
7 |
higher_val |
higher_val |
auto[1] |
21159 |
1 |
|
|
T7 |
42 |
|
T12 |
50 |
|
T8 |
21 |
higher_val |
lower_val |
auto[0] |
43571 |
1 |
|
|
T1 |
26 |
|
T2 |
47 |
|
T9 |
5 |
higher_val |
lower_val |
auto[1] |
21248 |
1 |
|
|
T7 |
29 |
|
T12 |
40 |
|
T8 |
17 |
higher_val |
zero_val |
auto[0] |
98 |
1 |
|
|
T36 |
1 |
|
T65 |
1 |
|
T109 |
1 |
higher_val |
zero_val |
auto[1] |
42862 |
1 |
|
|
T7 |
85 |
|
T12 |
84 |
|
T8 |
34 |
lower_val |
higher_val |
auto[0] |
42981 |
1 |
|
|
T1 |
24 |
|
T2 |
21 |
|
T9 |
5 |
lower_val |
higher_val |
auto[1] |
21026 |
1 |
|
|
T7 |
51 |
|
T12 |
57 |
|
T8 |
13 |
lower_val |
lower_val |
auto[0] |
43216 |
1 |
|
|
T1 |
30 |
|
T2 |
23 |
|
T9 |
2 |
lower_val |
lower_val |
auto[1] |
21374 |
1 |
|
|
T7 |
34 |
|
T12 |
32 |
|
T8 |
12 |
lower_val |
zero_val |
auto[0] |
99 |
1 |
|
|
T12 |
1 |
|
T11 |
1 |
|
T202 |
1 |
lower_val |
zero_val |
auto[1] |
42586 |
1 |
|
|
T7 |
96 |
|
T12 |
89 |
|
T8 |
25 |
zero_val |
higher_val |
auto[0] |
592 |
1 |
|
|
T1 |
1 |
|
T7 |
1 |
|
T9 |
1 |
zero_val |
higher_val |
auto[1] |
133 |
1 |
|
|
T41 |
4 |
|
T32 |
1 |
|
T203 |
1 |
zero_val |
lower_val |
auto[0] |
519 |
1 |
|
|
T2 |
1 |
|
T14 |
1 |
|
T37 |
1 |
zero_val |
lower_val |
auto[1] |
123 |
1 |
|
|
T17 |
1 |
|
T18 |
1 |
|
T203 |
1 |
zero_val |
zero_val |
auto[0] |
280 |
1 |
|
|
T12 |
1 |
|
T8 |
1 |
|
T36 |
1 |
zero_val |
zero_val |
auto[1] |
197 |
1 |
|
|
T17 |
1 |
|
T30 |
2 |
|
T32 |
1 |