Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10146	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	8943	1			T7	24		T12	19		T9	3
len_5001_7500	14588	1			T7	24		T12	18		T9	10
len_2501_5000	9160	1			T7	24		T12	18		T9	3
len_1025_2500	5383	1			T7	14		T12	11		T13	14
len_769_1024	6561	1			T1	34		T7	2		T12	2
len_513_768	7095	1			T1	30		T7	3		T12	2
len_257_512	21292	1			T1	37		T7	2		T12	2
len_0_256	254066	1			T1	31		T2	141		T7	211
len_keccak_block_sizes[72]	710	1			T7	2		T12	2		T13	2
len_keccak_block_sizes[104]	614	1			T7	2		T12	2		T13	2
len_keccak_block_sizes[136]	513	1			T12	2		T37	3		T108	2
len_keccak_block_sizes[144]	424	1			T37	3		T108	2		T33	2
len_keccak_block_sizes[168]	322	1			T37	3		T40	1		T203	3
len_1	747	1			T7	2		T12	2		T13	2
len_0	1205	1			T2	3		T7	2		T12	2