Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99960985	1			T1	21326		T2	1436		T7	161397
all_pins[1]	99960985	1			T1	21326		T2	1436		T7	161397
all_pins[2]	99960985	1			T1	21326		T2	1436		T7	161397

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	298993543	1			T1	63181		T2	4103		T7	483729
values[0x1]	889412	1			T1	797		T2	205		T7	462
transitions[0x0=>0x1]	886701	1			T1	797		T2	205		T7	462
transitions[0x1=>0x0]	886724	1			T1	797		T2	205		T7	462

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99456748	1			T1	21130		T2	1231		T7	160935
all_pins[0]	values[0x1]	504237	1			T1	196		T2	205		T7	462
all_pins[0]	transitions[0x0=>0x1]	504229	1			T1	196		T2	205		T7	462
all_pins[0]	transitions[0x1=>0x0]	6348	1			T8	63		T9	3		T10	45
all_pins[1]	values[0x0]	99954629	1			T1	21326		T2	1436		T7	161397
all_pins[1]	values[0x1]	6356	1			T8	63		T9	3		T10	45
all_pins[1]	transitions[0x0=>0x1]	5994	1			T8	63		T9	3		T10	45
all_pins[1]	transitions[0x1=>0x0]	378457	1			T1	601		T8	862		T10	383
all_pins[2]	values[0x0]	99582166	1			T1	20725		T2	1436		T7	161397
all_pins[2]	values[0x1]	378819	1			T1	601		T8	862		T10	383
all_pins[2]	transitions[0x0=>0x1]	376478	1			T1	601		T8	862		T10	383
all_pins[2]	transitions[0x1=>0x0]	501919	1			T1	196		T2	205		T7	462