Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	710	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5885	1			T1	17		T8	22		T9	5
len_601_800	13230	1			T1	46		T8	28		T9	3
len_401_600	8808	1			T1	29		T8	33		T9	6
len_201_400	16628	1			T1	9		T8	8		T9	6
len_65_200	72546	1			T1	7		T2	53		T8	3
len_min_for_xof_require_squeeze	992	1			T37	10		T41	1		T141	1
len_keccak_block_sizes[72]	731	1			T2	1		T37	5		T18	1
len_keccak_block_sizes[104]	745	1			T37	5		T141	2		T203	5
len_keccak_block_sizes[136]	724	1			T37	5		T141	2		T203	5
len_keccak_block_sizes[144]	277	1			T2	1		T10	1		T37	5
len_keccak_block_sizes[168]	274	1			T37	5		T17	1		T203	5
len_datapath_width	14158	1			T2	5		T8	1		T35	246
len_2_63	210789	1			T1	5		T2	79		T7	310
len_1	52	1			T2	4		T41	1		T18	1