Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11062453 |
1 |
|
|
T1 |
22420 |
|
T2 |
4838 |
|
T7 |
3720 |
auto[1] |
11062453 |
1 |
|
|
T1 |
22420 |
|
T2 |
4838 |
|
T7 |
3720 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21886418 |
1 |
|
|
T1 |
44658 |
|
T2 |
9482 |
|
T7 |
7440 |
triple_byte_access |
79514 |
1 |
|
|
T1 |
48 |
|
T2 |
54 |
|
T8 |
66 |
halfword_access |
79856 |
1 |
|
|
T1 |
62 |
|
T2 |
74 |
|
T8 |
52 |
byte_access |
79118 |
1 |
|
|
T1 |
72 |
|
T2 |
66 |
|
T8 |
80 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10943209 |
1 |
|
|
T1 |
22329 |
|
T2 |
4741 |
|
T7 |
3720 |
auto[0] |
triple_byte_access |
39757 |
1 |
|
|
T1 |
24 |
|
T2 |
27 |
|
T8 |
33 |
auto[0] |
halfword_access |
39928 |
1 |
|
|
T1 |
31 |
|
T2 |
37 |
|
T8 |
26 |
auto[0] |
byte_access |
39559 |
1 |
|
|
T1 |
36 |
|
T2 |
33 |
|
T8 |
40 |
auto[1] |
word_access |
10943209 |
1 |
|
|
T1 |
22329 |
|
T2 |
4741 |
|
T7 |
3720 |
auto[1] |
triple_byte_access |
39757 |
1 |
|
|
T1 |
24 |
|
T2 |
27 |
|
T8 |
33 |
auto[1] |
halfword_access |
39928 |
1 |
|
|
T1 |
31 |
|
T2 |
37 |
|
T8 |
26 |
auto[1] |
byte_access |
39559 |
1 |
|
|
T1 |
36 |
|
T2 |
33 |
|
T8 |
40 |