Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99755752	1			T1	2945		T3	2182		T6	23034
all_values[1]	99755752	1			T1	2945		T3	2182		T6	23034
all_values[2]	99755752	1			T1	2945		T3	2182		T6	23034

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

498222

1

T1

14

T3

69

T7

52

auto[1]

298769034

1

T1

8821

T3

6477

T6

69102

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

297744000

1

T1

8025

T3

6486

T6

68457

auto[1]

1523256

1

T1

810

T3

60

T6

645

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	171940	1			T7	18		T8	17		T9	2087
all_values[0]	auto[0]	auto[1]	1969	1			T7	4		T8	4		T9	10
all_values[0]	auto[1]	auto[0]	99076060	1			T1	2675		T3	2162		T6	22819
all_values[0]	auto[1]	auto[1]	505783	1			T1	270		T3	20		T6	215
all_values[1]	auto[0]	auto[0]	172167	1			T7	13		T8	14		T11	7
all_values[1]	auto[0]	auto[1]	1705	1			T7	2		T8	2		T11	1
all_values[1]	auto[1]	auto[0]	99075833	1			T1	2675		T3	2162		T6	22819
all_values[1]	auto[1]	auto[1]	506047	1			T1	270		T3	20		T6	215
all_values[2]	auto[0]	auto[0]	148901	1			T1	12		T3	68		T7	13
all_values[2]	auto[0]	auto[1]	1540	1			T1	2		T3	1		T7	2
all_values[2]	auto[1]	auto[0]	99099099	1			T1	2663		T3	2094		T6	22819
all_values[2]	auto[1]	auto[1]	506212	1			T1	268		T3	19		T6	215