Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
356144 |
1 |
|
|
T1 |
2 |
|
T3 |
52 |
|
T6 |
314 |
auto[1] |
335188 |
1 |
|
|
T1 |
356 |
|
T11 |
36 |
|
T12 |
144 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173448 |
1 |
|
|
T1 |
87 |
|
T3 |
18 |
|
T6 |
78 |
lower_val |
170690 |
1 |
|
|
T1 |
80 |
|
T3 |
12 |
|
T6 |
84 |
zero_val |
1836 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
261760 |
1 |
|
|
T1 |
90 |
|
T3 |
20 |
|
T6 |
184 |
lower_val |
261244 |
1 |
|
|
T1 |
88 |
|
T3 |
32 |
|
T6 |
130 |
zero_val |
168328 |
1 |
|
|
T1 |
180 |
|
T11 |
20 |
|
T12 |
84 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
44695 |
1 |
|
|
T3 |
7 |
|
T6 |
38 |
|
T7 |
44 |
higher_val |
higher_val |
auto[1] |
20877 |
1 |
|
|
T1 |
21 |
|
T11 |
2 |
|
T12 |
9 |
higher_val |
lower_val |
auto[0] |
44483 |
1 |
|
|
T3 |
11 |
|
T6 |
40 |
|
T7 |
30 |
higher_val |
lower_val |
auto[1] |
21073 |
1 |
|
|
T1 |
22 |
|
T11 |
2 |
|
T12 |
8 |
higher_val |
zero_val |
auto[0] |
78 |
1 |
|
|
T14 |
2 |
|
T32 |
1 |
|
T24 |
1 |
higher_val |
zero_val |
auto[1] |
42242 |
1 |
|
|
T1 |
44 |
|
T11 |
2 |
|
T12 |
28 |
lower_val |
higher_val |
auto[0] |
43872 |
1 |
|
|
T3 |
5 |
|
T6 |
49 |
|
T7 |
31 |
lower_val |
higher_val |
auto[1] |
20750 |
1 |
|
|
T1 |
23 |
|
T11 |
5 |
|
T12 |
13 |
lower_val |
lower_val |
auto[0] |
43915 |
1 |
|
|
T3 |
7 |
|
T6 |
35 |
|
T7 |
33 |
lower_val |
lower_val |
auto[1] |
20702 |
1 |
|
|
T1 |
16 |
|
T11 |
1 |
|
T12 |
6 |
lower_val |
zero_val |
auto[0] |
80 |
1 |
|
|
T9 |
1 |
|
T14 |
1 |
|
T23 |
1 |
lower_val |
zero_val |
auto[1] |
41371 |
1 |
|
|
T1 |
41 |
|
T11 |
7 |
|
T12 |
19 |
zero_val |
higher_val |
auto[0] |
516 |
1 |
|
|
T14 |
3 |
|
T77 |
1 |
|
T158 |
1 |
zero_val |
higher_val |
auto[1] |
134 |
1 |
|
|
T9 |
2 |
|
T14 |
1 |
|
T45 |
3 |
zero_val |
lower_val |
auto[0] |
578 |
1 |
|
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
zero_val |
lower_val |
auto[1] |
141 |
1 |
|
|
T14 |
3 |
|
T23 |
4 |
|
T90 |
1 |
zero_val |
zero_val |
auto[0] |
257 |
1 |
|
|
T1 |
1 |
|
T12 |
1 |
|
T9 |
2 |
zero_val |
zero_val |
auto[1] |
210 |
1 |
|
|
T9 |
2 |
|
T14 |
3 |
|
T76 |
2 |