Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

---

Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10269	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	9116	1			T1	39		T8	36		T9	32
len_5001_7500	14553	1			T1	90		T8	92		T9	93
len_2501_5000	9169	1			T1	22		T8	12		T9	14
len_1025_2500	5405	1			T1	7		T8	9		T9	11
len_769_1024	6371	1			T1	2		T3	3		T6	30
len_513_768	6802	1			T1	1		T3	2		T6	47
len_257_512	21090	1			T3	8		T6	30		T8	3
len_0_256	255856	1			T1	18		T3	1		T6	39
len_keccak_block_sizes[72]	715	1			T10	1		T76	3		T77	2
len_keccak_block_sizes[104]	620	1			T10	1		T76	3		T77	2
len_keccak_block_sizes[136]	525	1			T76	3		T77	2		T159	2
len_keccak_block_sizes[144]	422	1			T9	1		T76	3		T77	2
len_keccak_block_sizes[168]	320	1			T76	3		T160	3		T74	1
len_1	740	1			T7	3		T55	2		T76	3
len_0	1255	1			T1	4		T7	1		T8	3