Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99755752	1			T1	2945		T3	2182		T6	23034
all_pins[1]	99755752	1			T1	2945		T3	2182		T6	23034
all_pins[2]	99755752	1			T1	2945		T3	2182		T6	23034

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	298455936	1			T1	8563		T3	6523		T6	67804
values[0x1]	811320	1			T1	272		T3	23		T6	1298
transitions[0x0=>0x1]	809179	1			T1	272		T3	23		T6	1297
transitions[0x1=>0x0]	809209	1			T1	272		T3	23		T6	1298

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99249969	1			T1	2675		T3	2162		T6	22819
all_pins[0]	values[0x1]	505783	1			T1	270		T3	20		T6	215
all_pins[0]	transitions[0x0=>0x1]	505773	1			T1	270		T3	20		T6	215
all_pins[0]	transitions[0x1=>0x0]	6383	1			T1	2		T3	3		T6	68
all_pins[1]	values[0x0]	99749359	1			T1	2943		T3	2179		T6	22966
all_pins[1]	values[0x1]	6393	1			T1	2		T3	3		T6	68
all_pins[1]	transitions[0x0=>0x1]	6123	1			T1	2		T3	3		T6	68
all_pins[1]	transitions[0x1=>0x0]	298874	1			T6	1015		T14	1714		T10	10275
all_pins[2]	values[0x0]	99456608	1			T1	2945		T3	2182		T6	22019
all_pins[2]	values[0x1]	299144	1			T6	1015		T14	1714		T10	10295
all_pins[2]	transitions[0x0=>0x1]	297283	1			T6	1014		T14	1707		T10	10231
all_pins[2]	transitions[0x1=>0x0]	503952	1			T1	270		T3	20		T6	215