Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	653	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5691	1			T1	38		T3	2		T6	16
len_601_800	13046	1			T1	60		T3	8		T6	39
len_401_600	8581	1			T1	35		T3	2		T6	33
len_201_400	16622	1			T1	23		T6	11		T8	25
len_65_200	73301	1			T1	14		T3	2		T6	7
len_min_for_xof_require_squeeze	992	1			T9	2		T56	1		T76	9
len_keccak_block_sizes[72]	748	1			T7	1		T12	1		T9	1
len_keccak_block_sizes[104]	738	1			T7	1		T9	1		T55	2
len_keccak_block_sizes[136]	767	1			T55	1		T76	9		T158	1
len_keccak_block_sizes[144]	288	1			T7	1		T11	1		T9	1
len_keccak_block_sizes[168]	284	1			T7	1		T8	1		T11	1
len_datapath_width	13610	1			T6	2		T7	7		T11	1
len_2_63	212639	1			T1	7		T3	11		T6	8
len_1	59	1			T1	1		T7	1		T23	1