Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10894733 |
1 |
|
|
T1 |
29428 |
|
T3 |
2574 |
|
T6 |
23576 |
auto[1] |
10894668 |
1 |
|
|
T1 |
29428 |
|
T3 |
2574 |
|
T6 |
23576 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21550725 |
1 |
|
|
T1 |
58590 |
|
T3 |
5134 |
|
T6 |
46928 |
triple_byte_access |
79118 |
1 |
|
|
T1 |
82 |
|
T3 |
6 |
|
T6 |
64 |
halfword_access |
79848 |
1 |
|
|
T1 |
94 |
|
T3 |
6 |
|
T6 |
70 |
byte_access |
79710 |
1 |
|
|
T1 |
90 |
|
T3 |
2 |
|
T6 |
90 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10775395 |
1 |
|
|
T1 |
29295 |
|
T3 |
2567 |
|
T6 |
23464 |
auto[0] |
triple_byte_access |
39559 |
1 |
|
|
T1 |
41 |
|
T3 |
3 |
|
T6 |
32 |
auto[0] |
halfword_access |
39924 |
1 |
|
|
T1 |
47 |
|
T3 |
3 |
|
T6 |
35 |
auto[0] |
byte_access |
39855 |
1 |
|
|
T1 |
45 |
|
T3 |
1 |
|
T6 |
45 |
auto[1] |
word_access |
10775330 |
1 |
|
|
T1 |
29295 |
|
T3 |
2567 |
|
T6 |
23464 |
auto[1] |
triple_byte_access |
39559 |
1 |
|
|
T1 |
41 |
|
T3 |
3 |
|
T6 |
32 |
auto[1] |
halfword_access |
39924 |
1 |
|
|
T1 |
47 |
|
T3 |
3 |
|
T6 |
35 |
auto[1] |
byte_access |
39855 |
1 |
|
|
T1 |
45 |
|
T3 |
1 |
|
T6 |
45 |