Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99660480	1			T1	112813		T3	454912		T7	252
all_values[1]	99660480	1			T1	112813		T3	454912		T7	252
all_values[2]	99660480	1			T1	112813		T3	454912		T7	252

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

571500

1

T1

22

T3

52

T13

343

auto[1]

298409940

1

T1

338417

T3

136468

T7

756

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

297449400

1

T1

337302

T3

135454

T7

711

auto[1]

1532040

1

T1

1137

T3

10194

T7

45

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	186643	1			T1	9		T3	25		T13	169
all_values[0]	auto[0]	auto[1]	2191	1			T1	10		T3	16		T13	2
all_values[0]	auto[1]	auto[0]	98963157	1			T1	112425		T3	451489		T7	237
all_values[0]	auto[1]	auto[1]	508489	1			T1	369		T3	3382		T7	15
all_values[1]	auto[0]	auto[0]	194116	1			T3	5		T9	1609		T15	1
all_values[1]	auto[0]	auto[1]	1721	1			T3	6		T9	1		T16	2
all_values[1]	auto[1]	auto[0]	98955684	1			T1	112434		T3	451509		T7	237
all_values[1]	auto[1]	auto[1]	508959	1			T1	379		T3	3392		T7	15
all_values[2]	auto[0]	auto[0]	185144	1			T1	1		T13	170		T8	2375
all_values[2]	auto[0]	auto[1]	1685	1			T1	2		T13	2		T8	2
all_values[2]	auto[1]	auto[0]	98964656	1			T1	112433		T3	451514		T7	237
all_values[2]	auto[1]	auto[1]	508995	1			T1	377		T3	3398		T7	15