Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
344438 |
1 |
|
|
T1 |
492 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
350250 |
1 |
|
|
T3 |
4528 |
|
T9 |
88 |
|
T15 |
4 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173678 |
1 |
|
|
T1 |
116 |
|
T3 |
1110 |
|
T7 |
9 |
lower_val |
172576 |
1 |
|
|
T1 |
133 |
|
T3 |
1140 |
|
T7 |
2 |
zero_val |
1883 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
5 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
259762 |
1 |
|
|
T1 |
264 |
|
T3 |
1188 |
|
T7 |
8 |
lower_val |
259448 |
1 |
|
|
T1 |
228 |
|
T3 |
1120 |
|
T7 |
10 |
zero_val |
175478 |
1 |
|
|
T2 |
2 |
|
T3 |
2222 |
|
T9 |
46 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
43079 |
1 |
|
|
T1 |
63 |
|
T7 |
3 |
|
T13 |
47 |
higher_val |
higher_val |
auto[1] |
21941 |
1 |
|
|
T3 |
310 |
|
T9 |
5 |
|
T19 |
4 |
higher_val |
lower_val |
auto[0] |
43014 |
1 |
|
|
T1 |
53 |
|
T7 |
6 |
|
T13 |
51 |
higher_val |
lower_val |
auto[1] |
21833 |
1 |
|
|
T3 |
276 |
|
T9 |
4 |
|
T19 |
3 |
higher_val |
zero_val |
auto[0] |
98 |
1 |
|
|
T19 |
1 |
|
T66 |
2 |
|
T146 |
1 |
higher_val |
zero_val |
auto[1] |
43713 |
1 |
|
|
T3 |
524 |
|
T9 |
13 |
|
T19 |
9 |
lower_val |
higher_val |
auto[0] |
42636 |
1 |
|
|
T1 |
78 |
|
T7 |
1 |
|
T13 |
52 |
lower_val |
higher_val |
auto[1] |
21802 |
1 |
|
|
T3 |
277 |
|
T9 |
6 |
|
T19 |
2 |
lower_val |
lower_val |
auto[0] |
42601 |
1 |
|
|
T1 |
55 |
|
T7 |
1 |
|
T13 |
40 |
lower_val |
lower_val |
auto[1] |
21936 |
1 |
|
|
T3 |
266 |
|
T9 |
3 |
|
T19 |
2 |
lower_val |
zero_val |
auto[0] |
80 |
1 |
|
|
T11 |
1 |
|
T66 |
4 |
|
T38 |
1 |
lower_val |
zero_val |
auto[1] |
43521 |
1 |
|
|
T3 |
597 |
|
T9 |
12 |
|
T15 |
1 |
zero_val |
higher_val |
auto[0] |
561 |
1 |
|
|
T1 |
1 |
|
T7 |
1 |
|
T9 |
1 |
zero_val |
higher_val |
auto[1] |
145 |
1 |
|
|
T90 |
1 |
|
T66 |
1 |
|
T148 |
1 |
zero_val |
lower_val |
auto[0] |
605 |
1 |
|
|
T13 |
1 |
|
T8 |
1 |
|
T14 |
1 |
zero_val |
lower_val |
auto[1] |
122 |
1 |
|
|
T3 |
1 |
|
T90 |
1 |
|
T66 |
1 |
zero_val |
zero_val |
auto[0] |
257 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T19 |
1 |
zero_val |
zero_val |
auto[1] |
193 |
1 |
|
|
T3 |
3 |
|
T90 |
2 |
|
T11 |
1 |