Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99660480	1			T1	112813		T3	454912		T7	252
all_pins[1]	99660480	1			T1	112813		T3	454912		T7	252
all_pins[2]	99660480	1			T1	112813		T3	454912		T7	252

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	298124391	1			T1	338070		T3	136135		T7	741
values[0x1]	857049	1			T1	369		T3	3382		T7	15
transitions[0x0=>0x1]	854596	1			T1	369		T3	3382		T7	15
transitions[0x1=>0x0]	854620	1			T1	369		T3	3382		T7	15

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99151991	1			T1	112444		T3	451530		T7	237
all_pins[0]	values[0x1]	508489	1			T1	369		T3	3382		T7	15
all_pins[0]	transitions[0x0=>0x1]	508479	1			T1	369		T3	3382		T7	15
all_pins[0]	transitions[0x1=>0x0]	6455	1			T8	96		T9	19		T32	2
all_pins[1]	values[0x0]	99654015	1			T1	112813		T3	454912		T7	252
all_pins[1]	values[0x1]	6465	1			T8	96		T9	19		T32	2
all_pins[1]	transitions[0x0=>0x1]	6127	1			T8	96		T9	19		T32	2
all_pins[1]	transitions[0x1=>0x0]	341757	1			T13	23555		T16	12		T58	932
all_pins[2]	values[0x0]	99318385	1			T1	112813		T3	454912		T7	252
all_pins[2]	values[0x1]	342095	1			T13	23555		T16	12		T58	932
all_pins[2]	transitions[0x0=>0x1]	339990	1			T13	23403		T16	12		T58	932
all_pins[2]	transitions[0x1=>0x0]	506408	1			T1	369		T3	3382		T7	15