Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	703	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5608	1			T13	26		T8	26		T14	22
len_601_800	12868	1			T13	56		T8	77		T14	42
len_401_600	8473	1			T13	33		T8	47		T14	31
len_201_400	16605	1			T3	251		T13	21		T8	23
len_65_200	73946	1			T3	680		T13	6		T8	12
len_min_for_xof_require_squeeze	1006	1			T3	10		T8	1		T10	1
len_keccak_block_sizes[72]	757	1			T3	5		T8	1		T118	1
len_keccak_block_sizes[104]	756	1			T3	5		T32	1		T90	9
len_keccak_block_sizes[136]	753	1			T3	5		T90	9		T151	9
len_keccak_block_sizes[144]	290	1			T3	5		T197	5		T198	5
len_keccak_block_sizes[168]	288	1			T3	5		T118	1		T110	1
len_datapath_width	14124	1			T1	246		T3	5		T7	3
len_2_63	213344	1			T3	1329		T7	6		T13	48
len_1	65	1			T32	1		T118	3		T91	1