Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	101203063	1			T1	111241		T2	223576		T3	109760
all_values[1]	101203063	1			T1	111241		T2	223576		T3	109760
all_values[2]	101203063	1			T1	111241		T2	223576		T3	109760

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

609957

1

T1

14

T2

9

T3

7

auto[1]

302999232

1

T1

333709

T2

670719

T3

329273

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

302078712

1

T1

332604

T2

668967

T3

328158

auto[1]

1530477

1

T1

1119

T2

1761

T3

1122

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	199321	1			T1	3		T2	1		T7	586
all_values[0]	auto[0]	auto[1]	2257	1			T1	4		T2	2		T7	6
all_values[0]	auto[1]	auto[0]	100493583	1			T1	110865		T2	222988		T3	109386
all_values[0]	auto[1]	auto[1]	507902	1			T1	369		T2	585		T3	374
all_values[1]	auto[0]	auto[0]	226074	1			T1	3		T2	1		T3	5
all_values[1]	auto[0]	auto[1]	1745	1			T1	4		T2	2		T3	2
all_values[1]	auto[1]	auto[0]	100466830	1			T1	110865		T2	222988		T3	109381
all_values[1]	auto[1]	auto[1]	508414	1			T1	369		T2	585		T3	372
all_values[2]	auto[0]	auto[0]	179008	1			T2	1		T11	2		T13	14
all_values[2]	auto[0]	auto[1]	1552	1			T2	2		T11	1		T13	3
all_values[2]	auto[1]	auto[0]	100513896	1			T1	110868		T2	222988		T3	109386
all_values[2]	auto[1]	auto[1]	508607	1			T1	373		T2	585		T3	374