Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
359380 |
1 |
|
|
T1 |
492 |
|
T2 |
2 |
|
T3 |
492 |
auto[1] |
335180 |
1 |
|
|
T2 |
778 |
|
T14 |
16 |
|
T21 |
746 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173710 |
1 |
|
|
T1 |
120 |
|
T2 |
194 |
|
T3 |
135 |
lower_val |
171642 |
1 |
|
|
T1 |
110 |
|
T2 |
212 |
|
T3 |
120 |
zero_val |
1933 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
3 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
263546 |
1 |
|
|
T1 |
252 |
|
T2 |
200 |
|
T3 |
228 |
lower_val |
263090 |
1 |
|
|
T1 |
240 |
|
T2 |
186 |
|
T3 |
264 |
zero_val |
167924 |
1 |
|
|
T2 |
394 |
|
T14 |
14 |
|
T21 |
410 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
44951 |
1 |
|
|
T1 |
56 |
|
T3 |
63 |
|
T11 |
120 |
higher_val |
higher_val |
auto[1] |
21100 |
1 |
|
|
T2 |
53 |
|
T14 |
2 |
|
T21 |
35 |
higher_val |
lower_val |
auto[0] |
44625 |
1 |
|
|
T1 |
64 |
|
T3 |
72 |
|
T11 |
102 |
higher_val |
lower_val |
auto[1] |
21194 |
1 |
|
|
T2 |
40 |
|
T21 |
39 |
|
T35 |
16 |
higher_val |
zero_val |
auto[0] |
97 |
1 |
|
|
T120 |
1 |
|
T59 |
1 |
|
T79 |
1 |
higher_val |
zero_val |
auto[1] |
41743 |
1 |
|
|
T2 |
101 |
|
T14 |
8 |
|
T21 |
110 |
lower_val |
higher_val |
auto[0] |
44123 |
1 |
|
|
T1 |
61 |
|
T3 |
61 |
|
T11 |
95 |
lower_val |
higher_val |
auto[1] |
20731 |
1 |
|
|
T2 |
61 |
|
T21 |
47 |
|
T35 |
11 |
lower_val |
lower_val |
auto[0] |
44737 |
1 |
|
|
T1 |
49 |
|
T3 |
59 |
|
T11 |
95 |
lower_val |
lower_val |
auto[1] |
20574 |
1 |
|
|
T2 |
51 |
|
T21 |
38 |
|
T35 |
11 |
lower_val |
zero_val |
auto[0] |
91 |
1 |
|
|
T35 |
1 |
|
T63 |
1 |
|
T96 |
1 |
lower_val |
zero_val |
auto[1] |
41386 |
1 |
|
|
T2 |
100 |
|
T14 |
1 |
|
T21 |
113 |
zero_val |
higher_val |
auto[0] |
546 |
1 |
|
|
T11 |
3 |
|
T14 |
1 |
|
T8 |
1 |
zero_val |
higher_val |
auto[1] |
166 |
1 |
|
|
T22 |
3 |
|
T60 |
1 |
|
T79 |
1 |
zero_val |
lower_val |
auto[0] |
570 |
1 |
|
|
T1 |
1 |
|
T3 |
3 |
|
T12 |
1 |
zero_val |
lower_val |
auto[1] |
145 |
1 |
|
|
T22 |
3 |
|
T154 |
1 |
|
T162 |
1 |
zero_val |
zero_val |
auto[0] |
256 |
1 |
|
|
T2 |
1 |
|
T35 |
1 |
|
T62 |
1 |
zero_val |
zero_val |
auto[1] |
250 |
1 |
|
|
T22 |
2 |
|
T96 |
2 |
|
T154 |
1 |